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1 of 120 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales chann els. for information about device errata, click here: www.maxim - ic.com/errata . general description the ds26324 is a 16 - channel short - haul line interface unit (liu) that supports e1/t1/j1 from a single 3.3v power supply. a wide variety of applications are supported through internal impedance matching. a single bill o f material can support e1/t1/j1 that requires no external termination. redundancy is supported through nonintrusive monitoring, optimal high - impedance modes and configurable 1:1 or 1+1 backup enhancements. an on - chip synthesizer generates the e1/t1/j1 cloc k rates by a single master clock input of various frequencies. two clock output references are also offered. the device is offered in a 256 - pin te - csbga, the smallest package available for a 16- channel liu. applications t1 digital cross - connects atm and frame relay equipment wireless base stations isdn primary rate interface e1/t1/j1 multiplexer and channel banks e1/t1/j1 lan/wan routers functional diagram tneg rclk tpos tclk rpos rneg software control and jtag transmitter receiver loss 1 16 rtip rring jtag ttip tri ng features ? 16 e1, t1, or j1 short - haul line interface units ? independent e1, t1 or j1 selections ? fully internal impedance match requires no external resistors ? software - selectable transmit and receive- side impedance match ? crystal - less jitter attenuator ? selectable single - rail and dual- rail mode and ami or hdb3/b8zs line encoding and decoding ? detection and generation of ais ? digital/analog loss of signal detection as per t1.231, g.775 and ets 300 233 ? external master clock can be multiple of 2.048mhz or 1.544mhz for t1/j1 or e1 operation; this clock will be internally adapted for t1 or e1 usage ? receiver signal level indicator from - 2.5db to - 20db in 2.5db increments ? two built - in bert testers for diagnostics ? 8 - bit parallel interface support for intel or motorola mode or a 4 - wire serial interface ? transmit short - circuit protection ? g.77 2 nonintrusive monitoring ? receive monitor mode handles combinations of 14db to 20db of resistive attenuation along with 12db to 30db of cable attenuation ? specification compliance to the latest t1 and e1 standards ? single 3.3v supply with 5v tolerant i/o ? jtag boundary scan as per ieee 1149.1 ordering information part temp range pin - package DS26324G + 0c to +70c 256 te - csbga DS26324Gn + - 40c to +85c 256 te - csbga DS26324G 0c to +70c 256 te - csbga DS26324Gn - 40c to +85c 256 te - csbga +denotes a lead (pb) - free/rohs compliant package. demo kit available ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 19 - 5754; rev 3/11
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 2 of 120 table of contents 1 standards compliance ................................ ................................ ........................................ 6 1.1 t elecom s pecifications compli ance ................................ ................................ ....................... 6 2 detailed description ................................ ............................................................................ 7 3 block diagrams ................................ ................................ ...................................................... 8 4 pin description ................................ ................................ ...................................................... 10 5 functional descripti on ................................ ................................ ..................................... 17 5.1 p ort o pe ration ................................ ................................ ...................................................... 17 5.1.1 serial port operation ..................................................................................................................... 17 5.1.2 parallel port operation ................................................................................................................... 18 5.1.3 interrupt handling .......................................................................................................................... 18 5.2 p ower - u p and r eset ................................ ................................ .............................................. 19 5.3 m aster c lock ................................ ................................ ......................................................... 19 5.4 t ransmitter ................................................................ ................................ ............................ 20 5.4.1 transmit line templates ................................................................................................................ 22 5.4.2 liu transmit front - end .................................................................................................................. 25 5.4.3 transmit dual - rail mode ............................................................................................................... 26 5.4.4 transmit single - rail mode ............................................................................................................. 26 5.4.5 zero suppressi on? b8zs or hdb3 ................................................................................................ 26 5.4.6 transmit power - down.................................................................................................................... 26 5.4.7 transmit all ones .......................................................................................................................... 27 5.4.8 driver fail monitor .......................................................................................................................... 27 5.5 r eceiver ................................ ................................ .................................................................. 27 5.5.1 receiver impedance matching calibration ..................................................................................... 27 5.5.2 receiver monitor mode .................................................................................................................. 27 5.5.3 peak detector and slicer ............................................................................................................... 28 5.5.4 receive level in dicator .................................................................................................................. 28 5.5.5 clock and data recovery ............................................................................................................... 28 5.5.6 loss of signal ................................................................................................................................ 28 5.5.7 ais ................................................................................................................................................ 29 5.5.8 receive dual - rail mode ................................................................................................................ 29 5.5.9 receive single - rail mode .............................................................................................................. 30 5.5.10 bipolar violation and excessive zero detector ............................................................................... 30 5.6 j itter a ttenuator ................................ ................................ .................................................. 31 5.7 g.772 m onitor ................................ ................................ ................................ ........................ 32 5.8 l oopbacks ................................ ................................ ................................ ............................... 32 5.8.1 analog loopback ........................................................................................................................... 32 5.8.2 digital loopback ............................................................................................................................ 33 5.8.3 remote loopback .......................................................................................................................... 33 5.9 bert ................................................................ ................................ ........................................ 34 5.9.1 general description ....................................................................................................................... 34 5.9.2 configuration and monitoring ......................................................................................................... 35 5.9.3 receive pattern detection .............................................................................................................. 36 5.9.4 transmit pattern generation .......................................................................................................... 38 6 register maps and de finition ................................ ................................ .......................... 39 6.1 r egister d escription ................................ ................................ ............................................. 48 6.1.1 primary register bank ................................................................................................................... 48 6.1.2 secondary register bank ............................................................................................................... 63 6.1.3 individual liu register bank .......................................................................................................... 66 6.1.4 bert registers ............................................................................................................................. 84 7 jtag boundary scan a rchitecture and test access port .................................. 91 7.1 tap c ontroller s tate m achine ................................ ................................ ............................ 92 7.1.1 test -logic - reset ........................................................................................................................... 92 7.1.2 run- test - idle ................................................................................................................................. 92
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 3 of 120 7.1.3 select -dr- scan ............................................................................................................................. 92 7.1.4 capture -dr ................................................................................................................................... 92 7.1.5 shift -dr ......................................................................................................................................... 92 7.1.6 exit1 -dr ........................................................................................................................................ 92 7.1.7 pause -dr ...................................................................................................................................... 92 7.1.8 exit2 -dr ........................................................................................................................................ 92 7.1.9 update -dr..................................................................................................................................... 92 7.1.10 select -ir - scan ............................................................................................................................... 93 7.1.11 capture -ir ..................................................................................................................................... 93 7.1.12 shift -ir .......................................................................................................................................... 93 7.1.13 exit1 -ir .......................................................................................................................................... 93 7.1.14 pause -ir ....................................................................................................................................... 93 7.1.15 exit2 -ir .......................................................................................................................................... 93 7.1.16 update -ir ...................................................................................................................................... 93 7.2 i nstruction r egister ................................ ................................ ............................................. 95 7.2.1 extest ........................................................................................................................................ 95 7.2.2 highz ........................................................................................................................................... 95 7.2.3 clamp .......................................................................................................................................... 95 7.2.4 sample/preload ...................................................................................................................... 95 7.2.5 idcode ........................................................................................................................................ 95 7.2.6 bypass ........................................................................................................................................ 95 7.3 t est r egisters ................................ ................................ ....................................................... 96 7.3.1 boundary scan register ................................................................................................................ 96 7.3.2 bypass register ............................................................................................................................. 96 7.3.3 identification register .................................................................................................................... 96 8 dc electrical charac terization ................................ ................................ ................... 97 8.1 dc p in l ogic l evels ................................ ................................ ................................................ 97 8.2 s upply c urrent and o utput v oltage ................................ ................................ ................... 97 9 ac timing characteri stics ................................ ................................ ................................ 98 9.1 l ine i nterface c haracteristics ................................ ................................ ............................ 98 9.2 p arallel h ost i nterface t iming c haracteristics ................................ ................................ 99 9.3 s erial p ort ................................................................ ................................ ............................ 111 9.4 s ystem t iming ................................ ................................ ................................ ........................ 112 9.5 jtag t iming ................................ ................................ ............................................................ 114 10 pin configuration ................................ ................................ ................................................ 115 11 package information ................................ ......................................................................... 116 12 thermal information ................................ ......................................................................... 117 13 data sheet rev ision history ................................ ................................ ........................... 119
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 4 of 120 list of figures figure 3 - 1. block diagram ..................................................................................................................................... 8 figure 3 - 2. receive logic detail ............................................................................................................................ 9 figure 3 - 3. transmit logic detail ........................................................................................................................... 9 figure 5 - 1. serial port operation for write access ............................................................................................... 17 figure 5 - 2. serial port operation for read access with clke = 0 ........................................................................ 17 figure 5 - 3. serial port operation for read access with clke = 1 ........................................................................ 18 figure 5 - 4. interrupt handling flow diagram ........................................................................................................ 19 figure 5 - 5. prescaler pll and clock generator ................................................................................................... 20 figu re 5 - 6. t1 transmit pulse templates ............................................................................................................. 23 figure 5 - 7. e1 transmit pulse templates ............................................................................................................. 24 figure 5 - 8. liu front - end .................................................................................................................................... 25 figure 5 - 9. jitter attenuation ................................................................................................................................ 31 figure 5 - 10. analog loopback ............................................................................................................................. 32 figure 5 - 11. di gital loopback .............................................................................................................................. 33 figure 5 - 12. remote loopback ............................................................................................................................ 33 figure 5 - 13. prbs synchronization state diagram .............................................................................................. 36 figure 5 - 14. repetitive pattern synchronization state diagram ............................................................................ 37 figure 7 - 1. jtag functional block diagram ......................................................................................................... 91 figure 7 - 2. tap controller state diagram ............................................................................................................ 94 figure 9 - 1. intel nonmuxed read cycle ............................................................................................................. 100 figure 9 - 2. intel mux r ead cycle ....................................................................................................................... 101 figure 9 - 3. intel nonmux write cycle ................................................................................................................. 103 figure 9 - 4. intel mux write cycle ....................................................................................................................... 104 figure 9 - 5. motorola nonmux read cycle .......................................................................................................... 106 figure 9 - 6. motorola mux read cycle ................................................................................................................ 107 figure 9 - 7. moto rola nonmux write cycle .......................................................................................................... 109 figure 9 - 8. motorola mux write cycle ................................................................................................................ 110 figure 9 - 9. serial bus timing write operation.................................................................................................... 111 figure 9 - 10. serial bus timing read operation with clke = 0 .......................................................................... 111 figure 9 - 11. serial bus timing read operation with clke = 1 .......................................................................... 111 figure 9 - 12. transmitter systems timing ........................................................................................................... 112 figure 9 - 13. receiver systems timing ............................................................................................................... 113 figure 9 - 14. jtag timing .................................................................................................................................. 114 figure 10 - 1. 256- ball te - csbga ....................................................................................................................... 115
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 5 of 120 list of tables table 4 -1 . pin descriptions .................................................................................................................................. 10 table 5 - 1. parallel port mode selection and pin functions ................................................................................... 18 table 5 - 2. telecommunications specification c ompliance for ds26324 transmitters ........................................... 21 table 5 - 3. registers related to control of ds26324 transmitters ........................................................................ 21 table 5 - 4. template sel ections for short - haul mode ............................................................................................ 22 table 5 - 6. liu front - end values .......................................................................................................................... 26 table 5 - 7. loss criteria ansi t1.231, itu- t g.775, and ets 300 233 specifications .......................................... 28 table 5 - 8. ais criteria ansi t1.231, itu- t g.775, and ets 300 233 specifications ............................................ 29 table 5 - 9. ais detect ion and reset criteria for ds26324 ..................................................................................... 29 table 5 - 10. registers related to ais detection .................................................................................................... 29 table 5 - 11. bpv, code violation, and exc essive zero error reporting ................................................................. 30 table 5 - 12. pseudorandom pattern generation ................................................................................................... 35 table 5 - 13. repetitive pattern generation ............................................................................................................ 35 table 6 - 1. primary register set ........................................................................................................................... 40 table 6 - 2. secondary register set ....................................................................................................................... 41 table 6 - 3. individual liu register set .................................................................................................................. 42 table 6 - 4. bert register set .............................................................................................................................. 43 table 6 - 5. primary register set bit map .............................................................................................................. 44 table 6 - 6. secondary register set bit map .......................................................................................................... 45 table 6 - 7. individual liu register set bit map ..................................................................................................... 46 table 6 - 8. bert register bit map ....................................................................................................................... 47 table 6 - 9. g.772 monitoring control (liu 1) ......................................................................................................... 54 table 6 - 10. g.772 moni toring control (liu 9) ....................................................................................................... 54 table 6 - 11. tst template select transmitter register (lius 1? 8) ....................................................................... 59 table 6 - 12. tst template select tra nsmitter register (lius 9? 16) ..................................................................... 59 table 6 - 13. template selection ............................................................................................................................ 60 table 6 - 14. address pointer bank selection ........................................................................................................ 63 table 6 - 15. ds26324 mclk selections ............................................................................................................... 69 table 6 - 16. receiver sensitivity/monitor mode gain selection ............................................................................. 73 table 6 - 17. receiver signal level ........................................................................................................................ 75 table 6 - 18. bit error rate transceiver select for channels 1? 8 ........................................................................... 79 t able 6 - 19. bit error rate transceiver select for channels 9? 16 ......................................................................... 79 table 6 - 20. pll clock select ............................................................................................................................... 82 table 6 - 21. clock a select ................................................................................................................................... 82 table 7 - 1. instruction codes for ieee 1149.1 architecture ................................................................................... 95 table 7 - 2. id code structure ............................................................................................................................... 96 table 7 - 3. device id codes ................................................................................................................................. 96 table 8 - 1. recommended dc operating conditions ............................................................................................ 97 table 8 - 2. pin capa citance .................................................................................................................................. 97 table 8 - 3. dc characteristics .............................................................................................................................. 97 table 9 - 1. transmitter characteristics .................................................................................................................. 98 table 9 - 2. receiver characteristics ...................................................................................................................... 98 table 9 - 3. intel read mode characteristics .......................................................................................................... 99 table 9 - 4. intel writ e cycle characteristics ........................................................................................................ 102 table 9 - 5. motorola read cycle characteristics ................................................................................................. 105 table 9 - 6. motorola write cycle characteristics ................................................................................................. 108 table 9 - 7. serial port timing characteristics ...................................................................................................... 111 table 9 - 8. transmitter system timing ................................................................................................................ 112 table 9 - 9. receiver system timing.................................................................................................................... 113 table 9 - 10. jtag timing characteristics ........................................................................................................... 114 table 12 - 1. ther mal characteristics ................................................................................................................... 117 table 12 - 2. package power dissipation (for thermal considerations) ................................................................ 117 table 12 - 3. per - channel power -dow n savings (for thermal considerations) ..................................................... 118
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 6 of 120 1 standards compliance 1.1 telecom specifications compliance the ds26324 liu meets all the relevant latest telecommunications specifications. the following provides the t1 and e1 specifi cations and relevant sections that are applicable to the ds26324. ? t1 - related telecommunications specifications ? ansi t1.102: digital hierarchy electrical interface ? ansi t1.231: digital hierarchy - layer 1 in service performance monitoring ? ansi t1.403: netwo rk and customer installation interface - ds1 electrical interface ? g.736: characteristics of a synchronous digital multiplex equipment operating at 2048kbps ? g.823: the control of jitter and wander within digital networks which are based on the 2048kbps hiera rchy ? pub 62411: high capacity terrestrial digital service ? itu - t g.772: protected monitoring points provided on digital transmission systems ? e1 - related telecommunications specifications ? itu - t g.703: physical/electrical characteristics of g.703 hierarchic al digital interfaces ? itu - t g.736: characteristics of synchronous digital multiplex equipment operating at 2048kbps ? itu - t g.742: second order digital multiplex equipment operating at 8448kbps ? itu - t g.772: protected monitoring points provided on digital tra nsmission systems ? itu - t g.775: loss of signal (los) and alarm indication signal (ais) defect detection and clearance criteria ? ets 300 166: physical and electrical characteristics of hierarchical digital interfaces for equipment using the 2048kbps - based ple siosynchronous or synchronous digital hierarchies ? ets 300 233: integrated services digital network (isdn) ? g.736: characteristics of a synchronous digital multiplex equipment operating at 2048kbps ? g.823: the control of jitter and wander within digital netwo rks which are based on the 2048kbps hierarchy ? pub 62411: high capacity terrestrial digital service
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 7 of 120 2 detailed description the ds26324 is a single - chip, 16- channel, short - haul line interface unit for t1 (1.544mbps) and e1 (2.048mbps) applications. sixteen in dependent receivers and transmitters are provided in a single te - csbga package. the lius can be individually selected for t1, j1, or e1 operation. the liu requires a single master reference clock. this clock can be either 1.544mhz or 2.048mhz or multiples thereof, and either frequency can be internally adapted for t1, j1, or e1 mode. internal impedance matching provided for both transmit and receive paths reduces external component count. the transmit waveforms are compliant to g.703 and t1.102 specificatio n. the ds26324 provides software - selectable internal transmit termination for 100? t1 twisted pair, 110 ? j1 twisted pair, 120 ? e1 twisted pair, and 75 ? e1 coaxial applications. the transmitters have fast high - impedance capability and can be individually po wered down. the receivers can function with up to an 18db receive signal attenuation. a monitor gain setting also can be enabled to provide 14db and 20db. the ds26324 can be configured as a 14 - channel liu with channel 1 and 9 used for nonintrusive monitori ng in accordance with g.772. the receivers and transmitters can be programmed into single or dual - rail mode. ami or hdb3/b8zs encoding and decoding is selectable in single- rail mode. a 128- bit crystal - less on - board jitter attenuator for each liu can be pla ced in receive or transmit directions. the jitter attenuator meets the ets ctr12/13 itu - t g.736, g.742, g.823, and at&t pub 62411 specifications. the ds26324 detects and generates ais in accordance with t1.231, g.775, and ets 300 233. loss of signal is det ected in accordance with t1.231, g.775, and ets 300 233. the ds26324 can perform digital, analog, remote, and dual loopbacks on individual lius. jtag boundary scan is provided for the digital pins. the ds26324 can be configured using 8 - bit multiplexed or nonmultiplexed intel or motorola ports. a 4 - pin serial port selection is also available for configuration and monitoring of the device. the analog ami/hdb3 waveform of the e1 line or the ami/b8zs waveform of the t1 line is transformer coupled into the rtip and rring pins of the ds26324. the user can terminate the receive line using only internal termination that requires no external resistors. or, the user has the option to use partially internal impedance matching using a common 120 ? external resistor for e1, t1, and j1, and matching the line impedance internally to obtain 75 ? , 100 ? , 110 ? , or 120 ? termination values. note that fully internal impedance match requires a 1:1 transformer on the receive line. partially internal impedance matching supports either a 1:1 or a 1:2 transformer on the receive line. if a 1:2 transformer is used, the external termination resistor should be 30 ? . the ds26324 drives the e1 or t1 line from the ttip and tring pins by a 1:2 coupling transformer. the device recovers clock and d ata from the analog signal and passes it through a selectable jitter attenuator outputting the received line clock at rclk and data at rpos and rneg. the ds26324 receivers can recover data and clock for up to 18db of attenuation of the transmitted signals in t1 mode and 43db for e1 mode. receiver 1 can monitor the performance of receivers 2 to 8 or transmitters 2 to 8 . receiver 9 can monitor the performance of receivers 10 to 16 or transmitters 10 to 16. the ds26324 contains 16 identical transmitters. digi tal transmit data is input at tpos/tneg with reference to tclk. the data at these pins can be single - rail or dual - rail. this data is processed by waveshaping circuitry and the line driver to output at ttip and tring in accordance with ansi t1.102 for t1/j1 or g.703 for e1 mask.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 8 of 120 3 block diagrams figure 3 - 1 . block diagram line drivers optional termination filter peak detector clock/data recovery analog loopback csu filters wave shaping remote loopback (dual mode) local loopback jitter attenuator remote loopback receive logic transmit logic vco/pll mux unframed all ones insertion rring rtip tring ttip rpos/rdat rneg/cv rclk tpos/tdat tneg tclk master clock adapter jtag port control and interrupt port interface clke rdb/rwb rdy/ackb/sdo motel asb/ale/sclk a5/bswb a0 to a4 d0 to d7/ ad0 to ad7 csb intb trstb tms tclk tdi tdo mclk t1clk e1clk 16 16 typical of all 16 channels oe modesel wrb/dsb/sdi 8 5 reset rstb los reset t1clk e1clk ds26324
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 9 of 120 figure 3 - 2 . receive logic detail b8zs/hdb3/ami decoder (g.703, t1.102) bpvs, code violatiions (t1.231, o.161) ais detector g.775, etsi 300233, t1.231 excessive zero detect t1.231 mux all ones insert (ais) nrz data bpv/cv/exz rpos rneg/cv rclk los en srms iaisel aisel mclk ezde lascs pos neg rclk cvdeb encode encv lcs code encode figure 3 - 3 . transmit logic detail mux tpos/ tdata tneg/ bpv b8zs/hdb3/ami coder (g.703, t1.102) tclk bpv insert lcs code encode beir to remote loopback srms
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 10 of 120 4 pin description table 4 - 1 . pin descriptions name pin type function analog transmit and receive ttip1 e1 analog output transmit bipolar tip for channels 1 ? 16. these pins are di fferential line driver tip outputs. these pins can be high impedance if pin oe is low. when ?1? is set in the output enable register oe bit, the associated ttipn pin will be enabled when the oe pin is high. the differential outputs of ttipn and tringn can provide internal matched impedance for e1 75 ? , e1 120 ? , t1 100 ? , or j1 110 ? . if the tclk input for a given liu is held low for 64 mclks, that liu?s transmitter is powered down and the ttip/tring outputs are high impedance. ttip2 f1 ttip3 k1 ttip4 l1 ttip5 t5 ttip6 t6 ttip7 t10 ttip8 t11 ttip9 m16 ttip10 l16 ttip11 g16 ttip12 f16 ttip13 a12 ttip14 a11 ttip15 a7 ttip16 a6 tring1 e2 analog output transmit bipolar ring for channels 1 ? 16. these pins are differential line driver ring outputs. these pins can be high impedance if pin oe is low. when ?1? is set in the output enable register oe bit, the associated tringn pin will be enabled when the oe pin i s high. the differential outputs of ttipn and tringn can provide internal matched impedance for e1 75 ? , e1 120 ? , t1 100 ? , or j1 110 ? . if the tclk input for a given liu is held low for 64 mclks, that liu?s transmitter is powered down and the ttip/tring outp uts are high impedance. tring2 f2 tring3 k2 tring4 l2 tring5 r5 tring6 r6 tring7 r10 tring8 r11 tring9 m15 tring10 l15 tring11 g15 tring12 f15 tring13 b12 tring14 b11 tring15 b7 tring16 b6 rtip1 a1 analog input receive bipolar tip for channels 1 ? 16. receive analog input for differential receiver. data and clock are recovered and output at rpos/rneg and rclk pins, respectively. the differential inputs of rtipn and rringn can provide internal impedance matching wi th external resistance for e1 75 ? , e1 120 ? , t1 100 ? , or j1 110 ? . rtip2 c1 rtip3 h1 rtip4 n1 rtip5 t1 rtip6 t3 rtip7 t8 rtip8 t13 rtip9 t16 rtip10 p16 rtip11 j16 rtip12 d16 rtip13 a16 rtip14 a14 rtip15 a9 rtip16 a4
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 11 of 120 name pin type function resref r9 analog input resistor reference. if fully internal receive impedance match is selected, a 16k ? 1% resistor to gnd is needed. if not used, tie pin low. rring1 a2 analog input receive bipolar ring for channels 1 ? 16. receive analog input for d ifferential receiver. data and clock are recovered and output at rpos/rneg and rclk pins, respectively. the differential inputs of rtipn and rringn can provide internal impedance matching with external resistance for e1 75 ? , e1 120 ? , t1 100 ? , or j1 110 ? . rring2 c2 rring3 h2 rring4 n2 rring5 r1 rring6 r3 rring7 r8 rring8 r13 rring9 t15 rring10 p15 rring11 j15 rring12 d15 rring13 b16 rring14 b14 rring15 b9 rring16 b4 digital tx/rx tpos1/tdata1 f6 i transmit posit ive data input for channels 1 ? 6. when ds26324 is configured in dual - rail mode, the data input to tposn is output as a positive pulse on the line (tip and ring). transmit data input for channels 1 ? 16. when the device is configured in single - rail mode nrz da ta is input to tdatan. the data is sampled on the falling edge of tclkn and encoded hdb3/b8zs or ami before being output to the line. tpos2/tdata2 g7 tpos3/tdata3 j6 tpos4/tdata4 k6 tpos5/tdata5 l9 tpos6/tdata6 n5 tpos7/tdata7 p12 tpos8/ tdata8 m11 tpos9/tdata9 l11 tpos10/tdata10 j11 tpos11/tdata11 g11 tpos12/tdata12 c14 tpos13/tdata13 f9 tpos14/tdata14 e7 tpos15/tdata15 n12 tpos16/tdata16 d5 tneg1 c3 i transmit negative data for channels 1 ? 16. when ds26324 is co nfigured in dual - rail mode. the data input to tnegn is output as a negative mark on the line. tpos and tneg in dual - rail mode result in positive and negative pulses sent on the line: tneg2 j14 tneg3 j5 tneg4 g10 tneg5 m6 tneg6 p6 tneg7 p7 tposn tnegn output pulse tneg8 k9 0 0 space tneg9 l12 0 1 negative mark tneg10 j12 1 0 positive mark tneg11 h11 1 1 space tneg12 e13 tneg13 g8 tneg14 f7 tneg15 c6 tneg16 c5
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 12 of 120 name pin type function tclk1 f5 i transmit clock for channels 1 ? 16. the transmit c lock has to be 1.544mhz for t1 or 2.048mhz for e1 mode. tclkn is the clock used to sample the data tpos/tneg or tdat on the falling edge. the expected tclk can be inverted. if tclkn is ?high? for 16 or more mclks, then transmit all ones (taos) is sent to t he line side of the corresponding transmit channel. when tclkn starts clocking again, normal operation will begin again for the corresponding transmit channel. if tclkn is ?low? for 64 or more mclks, then the corresponding transmit channel on the line side will power - down and be put into high impedance. when tclkn starts clocking again the corresponding transmit channel will power - up and come out of high impedance. tclk2 g4 tclk3 g9 tclk4 h6 tclk5 m7 tclk6 l8 tclk7 l10 tclk8 p9 tclk9 k 11 tclk10 k12 tclk11 f14 tclk12 e12 tclk13 c11 tclk14 d12 tclk15 n7 tclk16 d11 rpos1/rdata1 f4 o, tri - state receive positive data output for channels 1 ? 16. in dual - rail mode the nrz data output indicates a positive pulse on rtip/rri ng. upon detecting an los, ais can be inserted if the aisel bit in the gc (0fh) register is set; otherwise, the pins will be active. ais insertion can also be controlled on an individual liu basis by the iaisel (05h) register. if a given receiver is in power - down mode, the associated rpos pin is high impedance. receive data output for channels 1 ? 16. in single - rail mode, nrz data is sent out on this pin. if a given receiver is in power - down mode, the associated rpos pin is high impedance. note: during an los condition, the rpos/rdata outputs remain active. rpos2/rdata2 f3 rpos3/rdata3 l3 rpos4/rdata4 l4 rpos5/rdata5 k8 rpos6/rdata6 m9 rpos7/rdata7 p8 rpos8/rdata8 m12 rpos9/rdata9 m14 rpos10/rdata10 k13 rpos11/rdata11 g12 rpos12/rdata12 e14 rpos13/rdata13 c12 rpos14/rdata14 c10 rpos15/rdata15 c8 rpos16/rdata16 e5 rneg1/cv1 e3 o, tri - state receive negative data output for channels 1 ? 16. in dua l - rail mode the nrz data output indicates a negative pulse on rtip/rring. upon detecting a los, ais can be inserted if aisel bit in the gc register is set; otherwise, the pins will be active. ais insertion can also be contr olled on an individual liu basis by iaisel register. if a given receiver is in power - down mode, the associated rneg pin is high impedance. code violation for channels 1 ? 16. in single - rail mode, bipolar violation, co de violation, and excessive zeros are reported on cvn. if hdb3 or b8zs is not selected, this pin indicates only bpvs. if a given receiver is in power - down mode, the associated cv pin is high impedance. rneg2/cv2 g5 rneg3/cv3 k4 rneg4/cv4 m3 rneg5 /cv5 l7 rneg6/cv6 m10 rneg7/cv7 p11 rneg8/cv8 k10 rneg9/cv9 m13 rneg10/cv10 l14 rneg11/cv11 f13 rneg12/cv12 f11 rneg13/cv13 e10 rneg14/cv14 c9 rneg15/cv15 c7 rneg16/cv16 j3
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 13 of 120 name pin type function rclk1 d3 o, tri - state receive clock for channe ls 1 ? 16. the receive data (rpos/rneg) is clocked out on the rising edge of rclk. if a given receiver is in power - down mode the rclk is high impedance. upon an los being detected, the rclk is switched from the recovered clock to mclk. rclk can be inverted b y the rclki register. rclk2 g6 rclk3 k3 rclk4 k5 rclk5 p5 rclk6 m8 rclk7 p10 rclk8 p13 rclk9 l13 rclk10 k14 rclk11 g13 rclk12 f12 rclk13 e8 rclk14 e9 rclk15 f8 rclk16 e6 mclk h12 i master clock. this is an inde pendent free - running clock that can be a multiple of 2.048mhz 50ppm for e1 mode or 1.544mhz 50ppm for t1 mode. the clock selection is available by mc bits mps0, mps1, freqs, and plle. a multiple of 2.048mhz can be interna l adapted to 1.544mhz and a multiple of 1.544mhz can be internal adapted to 2.048mhz. los1 d2 o loss -of - signal output. this output goes high when there is no transition on the received signal over a specified interval. the output will go low when there is sufficient ones density in the received signal. the los criteria for assertion and desertion criteria are described in section 5.5.6 . the los outputs can be configured to comply with t1.231, itu - t g.775, or ets 300 233. t1/e1 clock (teclk) (ball e11 only). this output becomes a t1 or e1 programmable clock output when enabled by register mc . for t1 or e1 frequency selection, see the ccr register. clock a (clka) (ball f10 only). this output becomes a programmable clock output when enabled by register mc . for frequency options, see ccr register. los2 g2 los3 j2 los4 m2 los5 r2 los6 t2 los7 r4 los8 r7 los9 r14 los10 n15 los11 k15 los12 h15 los13 b10 los14 b8 los15/teclk e11 los16/clka f10 host selection modesel a3 i mode selection. this pin is used to select the control mode of the ds26324 : low serial host mode high parallel host mode motel b3 i motorola intel select. when this pin is low, motorola mode is selected. when this pin is high intel mode is selected. csb p14 i chip select bar. this signal must be low during all accesses to the registers.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 14 of 120 name pin type function sclk/ale/asb n14 i shift clock. in the serial host mode, this pin is the serial clock. data on sdi is clocked on the rising edge of sclk. the data is clocked on sdo on the rising edge of sclk if clke is high. if clke is low the data on sdo is clocked on the falling edge of sclk. address latch enable. in parallel intel multiplexed mode, the address lines are latched on the falling edge of ale . address strobe bar. in parallel motorola multiplexed mode, the address is sampled on the falling edg e of asb . note: tie ale/asb pin high if using nonmuxed mode. rdb/rwb h14 i read bar. in intel host mode, this pin must be low for read operation. read write bar. in motorola mode, this pin is low for write operation and high for read operation. sdi/wrb/d sb g14 i serial data input. in the serial host mode, this pin is the serial input sdi; it is sampled on the rising edge of sclk. write bar. in intel host mode, this pin is active low during write operation. the data or address (multiplexed mode) is sampled on the rising edge of wrb. data strobe bar. in the parallel motorola mode, this pin is active low. during a write operation the data or address is sampled on the rising edge of dsb. during a read operation the data or address is driven on the rising edge of dsb. in the nonmultiplexed motorola mode the address bus (a[5:0]) is latched on the falling edge of dsb. sd0/rdyb/ackb c13 o serial data out. in serial host mode, the sdo data is output on this pin. if a serial write is in progress this pin is high imp edance. during a read sdo is high impedance when the sdi is in command/address mode. if clke is low sdo is output on the rising edge of sclk, if clke is high on the falling edge. ready bar output. a high on this pin reports to the host that the cycle is no t complete and wait states must be inserted. a low means the cycle is complete. acknowledge bar. in motorola parallel mode, a low on this pin indicates that the read data is available for the host or that the written data cycle is complete. intb d7 o, open drain interrupt bar (active low). this signal is tri - state when rstb pin is low. this interrupt signal is driven low when an event is detected on any of the enabled interrupt sources in any of the register banks. when there are no active and enabled int errupt sources, the pin can be programmed to either drive high or as open drain. the reset default is open drain when there are no active enabled interrupt sources. all interrupt sources are disabled when rstb = 0 and they must be programmed to be enabled.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 15 of 120 name pin type function d7/ad7 n3 i/o, tri - state data bus 7 ? 0. in nonmultiplexed host mode, these pins are the bidirectional data bus. address/data bus 7 ? 0. in multiplexed host mode, these pins are the bidirectional address/data bus. note: ad7 and ad6 do not carry address info rmation. in serial host mode, these pins should be grounded. d6/ad6 p3 d5/ad5 m4 d4/ad4 l5 d3/ad3 k7 d2/ad2 p4 d1/ad1 m5 d0/ad0 l6 a5/bswp e4 i address 5. in the host nonmultiplexed mode, this is the most significant bit of the addres s bus. bit swap. in serial host mode, this bit defines the serial data position to be msb first when low and lsb first when high. in multiplexed host mode, this pin should be grounded. a4 c4 i address bus 4 ? 0. these five pins are address pins in the paral lel host mode. in serial host mode and multiplexed host mode, these pins should be grounded. a3 h5 a2 g3 a1 h3 a0 n10 oe r12 i output enable. if this pin is pulled low all the transmitters outputs (ttip and tring) are high impedance. if pulled high all the transmitters are enabled when the associated output enable oe bit is set. if tst .rhpmc is set, the oe pin is granted control of the receiver internal termination. when oe is low, receiver internal termination will be high impedance. when oe is high, receiver termination will be enabled. the receiver can still monitor incoming signals even when termination is in high impedance. clke/mux t14 i clock edge. if clke is high, sdo i s clocked out on falling edge of sclk and if low sdo is on rising edge of sclk. multiplexed/nonmultiplexed select pin. when in parallel port mode, this pin is used to select multiplexed address and data operation or separate address and data. when mux is a high multiplexed address and data is used and when mux is low nonmultiplexed is used. jtag trstb e15 i, pullup jtag test port reset. this pin if low will reset the jtag port. if not used it can be left unconnected . tms b13 i, pullup jtag test m ode select. this pin is clocked on the rising edge of tck and is used to control the jtag selection between scan and test machine control. tck d14 i jtag test clock. the data tdi and tms are clocked on rising edge of tck and tdo is clocked out on the fall ing edge of tck. tdo a15 o, high - z jtag test data out. this is the serial output of the jtag port. the data is clocked out on the falling edge of tck. tdi b15 i, pullup test data input. this pin input is the serial data of the jtag test. the data on tdi is clocked on the rising edge of tck. this pin can be left unconnected.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 16 of 120 name pin type function reset rstb b5 i, pullup reset bar. this is the asynchronous reset input bar. it is internally pulled high. a 1 s low on this pin will reset the ds26324 registers to default value. power supplies dvdd h8, j9 i 3.3v digital power supply dvss h9, j8 i digital ground vddt1 d1 i, high -z 3.3v power supply for the transmitter. all vddt pins must be connected to vddt, which has to be 3.3v. vddt2 g1 vddt3 j1 vddt4 m1 vddt5 t4 vddt6 t7 vddt7 t9 vddt8 t12 vddt9 n16 vddt10 k16 vddt11 h16 vddt12 e16 vddt13 a13 vddt14 a10 vddt15 a8 vddt16 a5 gndt1 d4 i analog ground for transmitters gndt2 h4 gndt3 j4 gndt4 n4 gndt5 n6 gndt6 n8 gndt7 n9 gndt8 n11 gndt9 n13 gndt10 j13 gndt11 h13 gndt12 d13 gndt13 d10 gndt14 d9 gndt15 d8 gndt16 d6 avdd b1, c16, p1, r16, h7, j10 i 3.3v analog core power supply. decouple each pin separately. avss b2, c15, p2, r15, h10, j7 i analog core ground
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 17 of 120 5 functional descripti on 5.1 port operation 5.1.1 serial port operation setting modesel = ?low? enables the serial bus interface on the ds26324. port read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous re ads or writes by the host. see section 9.3 for the ac timing of the serial port. all serial port accesses are lsb first when bswp pin is high and msb first when bswp is low. figure 5 -1 to figure 5 -3 show operation with lsb first. this port is compatible with the spi interface defined for motorola processors. an example of this is the mmc2107 from motorola. reading or writing to the internal registers requires writing one address/command byte prior to transferring register data. the first bit written (lsb) of the address/command byte specifies whether the access is a read (1) or a write (0). the next 6 bits identify the register address (a1 to a6) (a7 is ignored). all data transfers are initiated by driving the csb input low. when clke is low, sdo data is output on the rising edge of sclk and when clke is high, data is output on the falling edge of sclk. data is hel d until the next falling or rising edge. all data transfers are terminated if csb input transitions high. port control logic is disabled and sdo is tri - stated when csb is high. sdi is always sampled on the rising edge of sclk. figure 5 - 1 . serial port operation for write access 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sclk csb 0 a1 a2 a3 a4 a5 a 6 x (adrs msb) sdi sdo d1 d2 d3 d4 d5 d7 (lsb) (msb) do d6 (lsb) write access enabled figure 5 - 2 . serial port operation for read access with clke = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 a1 a2 a3 a4 a5 d1 d2 d3 d4 d5 d6 sclk sdi sdo csb (lsb) (msb) d0 (lsb) d7 (msb) a6 x read access enabled
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 18 of 120 figure 5 - 3 . se rial port operation for read access with clke = 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 a1 a2 a3 a4 a5 d1 d2 d3 d4 d5 d6 sclk sdi sdo csb (lsb) (msb) d0 (lsb) d7 (msb) a6 x 5.1.2 parallel port operation when using the parallel interface on the ds26324 the user has the option for either multiplexed bus operation or nonmultiplexed bus operation. the ale pin is pulled high in nonm ultiplexed bus operation. the ds26324 can operate with either intel or motorola bus - timing configurations selected by motel pin. this pin being high selects the intel mode. the parallel port is only operational if modesel pin is pulled high. the following table lists all the pins and their functions in the parallel port mode. see the timing diagrams in section 9 for more details. table 5 - 1 . parallel port mode selecti on and pin functions modesel, motel, mux parallel host interface address, data, and control 100 nonmultiplexed motorola csb, ackb, dsb, rwb, asb, a[5:0], d[7:0], intb 110 nonmultiplexed intel csb, rdyb, wrb, rdb, ale, a[5:0], d[7:0], intb 101 multiplexe d motorola csb, ackb, dsb, rwb, asb, ad[7:0], intb 111 multiplexed intel csb, rdyb, wrb, rdb, ale, ad[7:0], intb 5.1.3 interrupt handling there are four sets of events that can potentially trigger an interrupt. the interrupt functions as follows: ? when status c hanges on an interruptible event, intb pin will go low if the event is enabled through the corresponding interrupt enable register. the intb has to be pulled high externally with a 10k ? resister for wired - or operation. if a wired- or operation is not requir ed, the intb pin can be configured to be high when not active by setting register gisc .intm . ? when an interrupt occurs the host processor has to read the interrupt status register to determine the source of the interrupt . the read will also clear the interrupt status register and this will clear the output intb pin. the interrupt status register can also be configured as clear on write as per register gisc .cwe . when set to clear on wri te, and interrupt status register bit (and the interrupt it generates) will only be cleared on writing a ?1? to it?s bit location in the interrupt status register. this makes is possible to clear interrupts on some bits in a register without clearing them on all bits. ? subsequently the host processor can read the corresponding status register to check the real - time status of the event.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 19 of 120 figure 5 - 4 . interrupt handling flow diagram interrupt allowed interrupt conditon exist? read interrupt status register read corresponding status register (optional) service the interrupt no yes 5.2 power - up and reset internal power_on_reset circuitry generates a reset during power - up. all registers are reset to the default values. writing to the software reset register generates at least 1 s reset cycle, which has the same effect as the power - up reset. the ds26324 can be reset by a low going pulse on the rstb pin (see table 4 -1 ). a reset can also be performed in software by writing any value to the swr register. 5.3 master clock the ds26324 requi res 2.048mhz 50ppm or 1.544mhz 50ppm or multiple thereof. the receiver uses the mclk as a reference for clock recovery, jitter attenuation and generating rclk during los. the ais ttransmission uses mclk for transmit all ones condition. see register mc to set desired incoming frequency. when the plle bit is set, the master clock adapter will generate both 2.048mhz (e1) and 1.544mhz (t1) clocks. if the plle bit is clear, both internal reference clocks will track mclk. mclk o r rclk can also be used to output clka on the los16 pin. register ccr is used to select the clock generated for clka and the teclk. any rclk can also be selected as an input to the clock generator using this same register . for a detailed description of selections available see figure 5 -5 .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 20 of 120 figure 5 - 5 . prescaler pll and clock generator pre scaler pll clk gen e1clk t1clk freqs mps1..0 plle rlck9..16 pclks2..0 pclks2..0 pclki1..0 rlck1..8 plle clka3..0 clka los16 rlos16 clkae los15 rlos15 teclke teclk teclks mclk 5.4 transmitter nrz data arrives on tpo s and tneg on the transmit system side. the tpos and tneg data is sampled on the falling edge of tclk. the data is encoded with hdb3 or b8zs or ami encoding when single - rail mode is selected (only tpos as the data source). when in single - rail mode only, bp v errors can be inserted for test purposes by register beir . pre - encoded data is expected when dual - rail mode is selected. the encoded data passes through a jitter attenuator if it is enabled for the transmit path. a di gital sequencer and dac are used to generate transmit waveforms compliant with t1.102 and g.703 pulse masks. the line driver supports internal impedance matching for 75 ? , 100 ? , 110 ? , and 120 ? modes. the ds26324 drivers have short and open circuit driver f ail monitor detection. there is an oe pin that can high impedance the transmitter outputs for protection switching when low. the individual transmitters are by default in high impedance. the oe register is used to enable th e transmitters individually when the oe pin is high. the ds26324 has to have the transmitter?s enabled by setting the register and then pulling the oe pin high. the registers that control the transmitter operation are shown in table 5 -2 .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 21 of 120 table 5 - 2 . telecommunications specification compliance for ds26324 transmitters transmitter function telecommunications compliance ami coding, b8zs substitution, ds1 electrica l interface ansi t1.102 t1 telecom pulse mask compliance ansi t1.403 t1 telecom pulse mask compliance ansi t1.102 transmit electrical characteristics for e1 transmission and return loss compliance itu - t g.703 table 5 - 3 . registers related to control of ds26324 transmitters register name function transmit all ones enable taoe transmit all ones enable. driver fault monitor status dfms driver fault status. driver fault monitor interrupt enable dfmie driver fault status interrupt mask. driver fault monitor interrupt status dfmis driver fault status interrupt m ask. automatic transmit all ones select ataos transmit all ones enabled automatically on los. global configuration gc global control of jitter attenuator, line coding and short circu it protection. template select transmitter tst the transmitter that the template select transmitter register applies to. template select ts the ts2 to ts0 bits for selection of the templ ates for transmitter and timpoff and timprim bits to control transmit impedance match. output enable configuration oe these register bits can be used to enable the transmitter outputs. master clock selection mc selects the mclk frequency used for transmit and receive. single - rail mode select srms this register can be used to select between single - rail and dual - rail mode. line code selection lcs the individual transceiver line codes can be selected to overwrite the global setting. transmit power - down enable tpde individual transmitters can be powered down. individual jitter atte nuator enable ijae enables the jitter attenuator. individual jitter attenuator position select ijaps selects whether jitter attenuator is in transmit or receive path individual j itter attenuator fifo depth select ijafds selects depth of jitter attenuator fifo. individual jitter attenuator fifo limit trip ijaflt indicates jitter attenuator fifo withi n 4 bits of its useful limit. individual short - circuit protection disable iscpd this register allows the individual transmitters to have short - circuit protection disable. bit error rate tester control btcr this register allows mapping of the internal berts into an individual transmit path. transmit clock invert tclki inverts tclk input. bpv error insertion b eir inserts a bipolar error in the transmit path when in single - rail mode.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 22 of 120 5.4.1 transmit line templates the ds26324 transmitters can be selected individually to meet the pulse masks for e1 and t1/j1 mode. the t1/j1 pulse mask is shown in the transmit pul se template and can be configured on an individual liu basis. the transmit template is selected via the ts2 - ts0 bits in the ts register. transmit impedance matching is selected using the timpoff and the timprm bits of the s ame register. when transmit impedance matching is enabled timprm will select between 75 ? and 120? impedance if an e1 template is selected, and between 100 ? and 110? impedance if a t1/j1 template is selected. in e1 mode, if 75 ? is selected via the timprm bi t, the output pulse amplitude will be 2.37v, if 120 ? is selected via the timprim bit, the output pulse amplitude will be 3.0v. the e1 pulse template is shown in figure 5 -7 and the t1 pulse template is sho wn in figure 5 -6 . table 5 - 4 . template selections for short - haul mode ts2, ts1, ts0 application 000 e1 001 reserved 010 011 dsx - 1 (0 ? 133ft) 100 dsx - 1 (1 33 ? 266ft) 101 dsx - 1 (266 ? 399ft) 110 dsx - 1 (399 ? 533ft) 111 dsx - 1 (533 ? 655ft)
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 23 of 120 figure 5 - 6 . t1 transmit pulse templates 1 .2 0 -0 .1 -0 .2 -0 .3 -0 .4 -0 .5 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1 .0 1 .1 -500 -300 -100 0 300 500 700 -400 -200 200 400 600 100 t im e (n s ) normali zed ampli tude t1.102/87, t1.403, cb 119 (oct. 79), & i.431 template -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 -500 -255 -175 -175 -75 0 175 225 600 750 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.16 -500 -150 -150 -100 0 100 150 150 300 430 600 750 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05 ui t im e am p. maximum curve ui t im e am p. minimum curve -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.34 0.77 1.16 -500 -255 -175 -175 -75 0 175 225 600 750 0.05 0.05 0.80 1.20 1.20 1.05 1.05 -0.05 0.05 0.05 -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.61 0.93 1.16 -500 -150 -150 -100 0 100 150 150 300 430 600 750 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.26 -0.05 -0.05 ui t im e am p. maximum curve ui t im e am p. minimum curve dsx-1 tem plate (per ansi t1.102 -1993) ds1 tem plate (per ansi t1.403 -1995)
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 24 of 120 figure 5 - 7 . e1 transmit pulse tem plates 0 -0.1 -0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 time (ns) scaled amplitude 50 100 150 200 250 -50 -100 -150 -200 -250 269ns 194ns 219ns (in 75 ohm systems, 1.0 on the scale = 2.37vpeak in 120 ohm systems, 1.0 on the scale = 3.00vpeak) g.703 template
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 25 of 120 5.4.2 liu transmit front - end it is recommended that the liu for the transmitter be configured as described in figure 5 -8 and in table 5 -5 . figure 5 - 8 . liu front - end optional termination c1 (one channel) ttip tring rtip rring dt dt dt dt ct 1:2 tft 1:1 or 1:2 tfr tx line rx line vddtn gndtn tvs1 3.3v c2 3.3v c3 avddn avssn 3.3v c4 rt c5 rt a110 a100 a75 dt dt dt dt
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 26 of 120 table 5 - 5 . liu front - end values mode component 75 ? coax, 120 ? twisted pair, 100/110 ? twisted pair tx capacitance ct 560pf typical. adjust for board parasitics for optimal return loss. tx protection dt 1 international rectifier 11dq04 or 10bq060, motorola mbr0540t1 rx transformer rtr 1:1 tfr pulse tx1 475 tx transformer 1:2 tft halo tg83 - s005nu rx transformer rtr 1:2 tfr pulse t1124 (0c to +70c), pulse t1114 ( - 40c to 85c) tx transformer 1:2 tft tx decoupling (tvddn) c1 common decoupling for all 16 channels = 68 f. tx decoupling (tvddn) c2 reco mmended decoupling per channel = 0.1 f. rx decoupling (avdd) c3 common decoupling for all 16 channels = 68 f. rx decoupling (avdd) c4 decouple all six pins separately with a 0.1 f capacitor. rx termination c5 1 rx capacitance for all 16 channels = 0.1 f. rx termination rtr 1:1 rt 1 need two resistors = 60.4 ? 1%. rx termination rtr 1:2 rt 1 need two resistors = 15.0 ? 1%. voltage protection tvs1 sgs - thomson smlvt 3v3 (3.3v transient suppressor) 1 only use if necessary for application. 5.4.3 transmit dual - ra il mode transmit dual - rail mode consists of the tpos, tneg, and tclk pins on the system side. nrz data is sampled on the falling edge of tclk as shown in figure 9 -12 . b8zs or hdb3 encoding is not availab le in transmit dual - rail mode. the data that appears on the tpos and tneg pins is output on ttip and tring without any modification. the single - rail mode select register ( srms ) is used for selection of dual - rail or sing le - rail mode. the data that arrives at the tpos and tneg can be overwritten in the maintenance mode by setting the bert control register ( btcr ). 5.4.4 transmit single - rail mode transmit single - rail mode consists of the tpos a nd tclk pins on the system side (tneg is not used.). nrz data is sampled on the falling edge of tclk as shown in figure 9 -12 . the zero substitution b8zs or hdb3 encoding is allowed. the tpos data is enco ded in ami or b8zs/hdb3 format on the ttip and tring pins after pulse shaping. the single - rail mode select register ( srms ) is used for selection of dual - rail or single- rail mode. the data that arrives at the tpos can be overwritten in the maintenance mode by setting in bit error rate tester control register ( btcr ). 5.4.5 zero suppression ? b8zs or hdb3 b8zs coding is available when the device is in t1 mode (selected by ts2, ts1 and ts0 bits i n the ts register). b8zs/hdb3 coding are enabled by default in single - rail mode. setting the lcs bit in the lcs register disables b8zs/hdb3. note that if the individual liu is configured i n e1 mode then hdb3 code substitution will be selected. bipolar violations can be inserted via the beir register only if b8zs or hdb3 coding is turned off. b8zs substitution is defined in ansi t1.102 and hdb3 in itu - t g .703 standards. 5.4.6 transmit power - down the transmitter will be powered down if the relevant bits in the tpde are set. the ttip/tring outputs will be high impedance when tpde is set.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 27 of 120 5.4.7 transmit all ones when transmit all ones is invoked, continuous ones are transmitted using mclk as the timing reference. data input at tpos and tneg is ignored. transmit all ones can be sent by setting bits in the taoe register. also, transmit all ones will b e enabled if bits in ataos are set and the corresponding receiver goes into los state in status register loss . 5.4.8 driver fail monitor the driver fail monitor is connected to the ttip and tring pins. it will detect a short or open circuit on the secondary side of the transmit transformer. the drive current will be limited to 50ma if a short circuit is detected. the dfms status registers and the corre sponding interrupt and enable registers can be used to monitor the driver failure. 5.5 receiver the ds26324?s 16 receivers are all identical. a 1:2 or 1:1 transformer can be used on the receive side (selected by the rtr bit), but only a 1:1 transformer can be used if fully internal impedance match is enabled. fully internal receive impdeance match does not require the use of any external resistor on the receive line. if partially internal impdeance matching is selected, the ds26334 will need only an external 12 0 ? resistor (30 ? for a 1:2 transformer) for e1, t1, and j1. the receive impedance match settings are controlled by the transmit template/impedance selection. see figure 5 -8 and table 5 -5 for external component values. partially internal impedance matching is enabled via the ts .rimpon bit. fully internal impedance matching is enabled by setting gc .rimpms and ts .rimpon. the peak detector and data slicer process the received signal. the output of the data slicer goes to clock and data recovery. a 2.048/1.544 pll is internally multiplied by 16 via another internal p ll and fed to the clock recovery system derives e1 or t1 clock. the clock recovery system uses the clock from the pll circuit to form a 16 times oversampler, which is used to recover the clock and data. this oversampling technique offers outstanding perfor mance to meet jitter tolerance specifications. b8zs/hdb3/ami decoding is available when single - rail mode is selected. the selection of single- rail or dual rail is done by settings in the srms register. the receiver is c apable of recovering signals up to 18db worth of attenuation. the receiver contains functionality to provide resistive gain up to 20db for monitor mode. three receive termination modes are available: 1) external impedance matching. internal impedance matching is disabled, external resistor should match line impedance. 2) partially internal impedance matching. internal impedance matching is enabled, in parallel with an external termination resistor (one value for all terminations). 3) fully internal impedance matchin g. internal impedance matching is enabled, no external termination necessary. this mode requires a 1:1 receive - side transformer. 5.5.1 receiver impedance matching calibration in fully internal impedance matching mode, calibration of the internal resistors is nec essary to match the line impedance accurately. calibration must be done upon power - up of the device. the resistance of the internal resistors does vary across temperature. therefore, it may be necessary to recalibrate if the ambient temperature changes mor e than 30 c. the user may conclude that it is necessary to recalibrate on a periodic basis if he expects such temperature swings. calibration is not necessary for partially internal impedance match mode. 5.5.2 receiver monitor mode the receive equalizer is equip ped with monitor mode function that allows for resistive gain up to 20db, along with cable attenuation of 6db to 24db as shown in the rsmm1 ? 4 registers.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 28 of 120 5.5.3 peak detector and slicer the slicer determines the polarity and p resence of the received data. the output of the slicer is sent to the clock and data recovery circuitry for extraction of data and clock. the slicer has a built - in peak detector for determination of the slicing threshold. 5.5.4 receive level indicator the ds263 24 will report the signal strength at rtip and rring in increments described in table 6 -17. via register bits cnrl3 ? c n rl0 located in the rsl1 ? 4 registers. 5.5.5 clock and da ta recovery the resultant e1 or t1 clock derived from the 2.048/1.544 pll is internally multiplied by 16 via another internal pll and fed to the clock recovery system. the clock recovery system uses the clock from the pll circuit to form a 16 times oversam pler, which is used to recover the clock and data. this oversampling technique offers outstanding performance to meet jitter tolerance specifications. 5.5.6 loss of signal the ds26324 uses both the digital and analog loss - detection method in compliance with the latest ansi t1.231 for t1/j1 and itu - t g.775 or ets 300 233 for e1 mode of operation. los is detected if the receiver level falls bellow a threshold analog voltage for certain duration. alternatively, this can be termed as having received ?zeros? for cert ain duration. the signal level and timing duration are defined in accordance with the ansi t1.231, itu - t g.775, or ets 300 233 specifications. the loss detection thresholds are based on cable loss of 18db for both t1 and e1 modes. rclk is replaced by mclk when the receiver detects a loss of signal. if the aisel bit is set in the gc register or the iaisel bit is set, the rpos/rneg data is replaced by ais. the loss state is exited when the receiver detects a certain number of ones density at a higher signal level than the loss detection level. the loss detection signal level and loss reset signal level are defined with a hysteresis to prevent the receiver from bouncing between ?los? and ?no los? states. table 5 -6 outlines the specifications governing the loss function. table 5 - 6 . loss criteria ansi t1.231, itu - t g.775, and ets 300 233 specif ications criteria standard t1.231 itu - t g.775 ets 300 233 loss detection criteria no pulses are detected for 175 75 bits. no pulses are detected for duration of 10 to 255 bit periods. no pulses are detected for a duration of 2048 bit periods or 1ms. l oss reset criteria loss is terminated if a duration of 12.5% ones are detected over duration of 175 75 bits. loss is not terminated if 8 consecutive zeros are found if b8zs encoding is used. if b8zs is not used loss is not terminated if 100 consecutive pu lses are zero. the incoming signal has transitions for duration of 10 to 255 bit periods. loss reset criteria is not defined.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 29 of 120 5.5.6.1 ansi t1.231 for t1 and j1 modes loss is detected if the received signal level is less than 200mv for duration of 192 bit periods . los is reset if the all of the following criteria are met: ? 24 or more ones are detected in 192 - bit period with a detection threshold of 300mv measured at rtip and rring. ? during the 192 bits less than 100 consecutive zeros are detected. ? 8 consecutive zero s are not detected if b8zs is set. 5.5.6.2 itu - t g.775 for e1 modes los is detected if the received signal level is less than 200mv for a continuous duration of 192 bit periods. los is reset if the receive signal level is greater than 300mv for a duration of 192 b it periods. 5.5.6.3 ets 300 233 for e1 modes los is detected if the received signal level is less than 200mv for a continuous duration of 2048 (1ms) bit periods. los is reset if the receive signal level is greater than 300mv for a duration of 192 bit periods. 5.5.7 ais table 5 -7 outlines the ds26324 ais related specifications. table 5 -8 states the ais functionality in the ds26324. the registers related to the ais detectio n are shown in table 5 -9 . table 5 - 7 . ais criteria ansi t1.231, itu - t g.775, and ets 300 233 specifications criteria standard itu - t g.775 for e1 ets 300 233 f or e1 ansi t1.231 for t1 ais detection criteria 2 or fewer zeros in each of 2 consecutive 512 - bit stream received. fewer than 3 zeros detected in 512 bit period. fewer than 9 zeros detected in a 8192- bit period (a ones density of 99.9% over a period of 5. 3ms) are received. ais clearance criteria 3 or more zeros in each of 2 consecutive 512 - bit streams received. 3 or more zeros in 512 bits received. 9 or more zeros detected in a 8192- bit period are received. table 5 - 8 . ais detection and reset criteria for ds26324 criteria standard itu - t g.775 for e1 ets 300 233 for e1 ansi t1.231 for t1 ais detection criteria 2 or fewer zeros in each of 2 consecutive 512 - bit streams received. fewer than 3 zeros detected in 512- bit period. fewer than 9 zeros contained in 8192 bits. ais clearance criteria 3 or more zeros in each of 2 consecutive 512 - bit streams received. 3 or more zeros in 512 bits received. 9 or more bits received in a 8192- bit stream. table 5 - 9 . registers related to ais detection register name functionality los/ais criteria selection lascs section criteria for ais (t1.231, g.775, ets 300 233 for e1). alarm indication s ignal status ais set when ais is detected. ais interrupt enable aisie if reset, interrupt due to ais is not generated. ais interrupt status aisis latched if there is a change in ais and the interrupt is enabled. 5.5.8 receive dual - rail mode receive dual - rail mode consists of the rpos, rneg, and rclk pins on the system side. in receive dual - rail mode, b8zs and hdb3 decoding is not available. the data that appears on the rtip and rring pins is output on rpos and rneg without any modification. the single - rail mode select register ( srms ) is used for selection of
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 30 of 120 dual - rail or single- rail mode. the bipolar violation (an d b8zs/hdb3) detectors detect violations in dual - rail and single - rail modes, but in dual - rail mode the violations will only be reported to the line violation detect status ( lvds ) registers. 5.5.9 receive single - rail mode rece ive single - rail mode consists of the rpos, rclk, and cv pins on the system side. b8zs or hdb3 decoding is available. the single - rail mode select register ( srms ) is used for selection of dual - rail or single- rail mode. 5.5.10 bi polar violation and excessive zero detector the ds26324 detects hdb3 code violations, bpvs, and excessive zero errors. the reporting of the errors is done through the rnegn/cvn pin in single - rail mode and the lvds regis ters in both single - and dual - rail modes. code violations are only detected in e1 mode with hdb3 encoding. the code violation detection declares an error when a bipolar violation of the same polarity as the last bipolar violation is received. excessive zer os are detected if eight consecutive zeros are detected with b8zs enabled and four consecutive zeros are detected with hdb3 enabled. excessive zero detection is enabled via the excessive zero detect enable register ( ezde ) and when hdb3/b8zs encoding/decoding is selected via the line code selection register ( lcs ). the bits in the lcs , ezde , and cvdeb registers determine the combinations that are reported. table 5 -10 outlines the functionality. table 5 - 10 . bpv, code violation, and exc essive zero error reporting conditions errors detected lcs ezde cvdeb 0 0 0 bpv (t1)/code violation (e1) 0 0 1 bpv 0 1 0 excessive zeros and bpv (t1)/code violation (e1) 0 1 1 excessive zeros and bpv 1 x x bpv
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 31 of 120 5.6 jitter attenuator the ds26324 contains an on - board jitter attenuator that can be set to a depth of either 32 or 128 bits via the jads bit in register gc . i t can also be controlled on an individual liu basis by settings in the ijafds register. the 128 - bit mode is used in applications where large excursions of wander are expected. the 32- bit mode is used in delay sensitive applications. the characteristics of the attenuation are shown in figure 5 -9 . the jitter attenuator can be placed in either the receive path or the transmit path or none by appropriately setting the japs and the jae bits in register gc . these selections can be changed on an individual liu basis by settings in the ijaps and ijae . in order fo r the jitter attenuator to operate properly, a 2.048mhz clock or multiple thereof, or 1.544mhz clock or multiple thereof, must be applied at mclk. itu - t specification g.703 requires an accuracy of 50ppm for both t1 and e1 applications. at&t pub 62411 and ansi specs require an accuracy of 32ppm for t1 interfaces. on - board circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the tclk pin to create a smooth jitter - free clock, which is used to clock data out of the jitter attenuator fifo. it is acceptable to provide a jittery clock at the tclk pin if the jitter attenuator is placed on the transmit side. if the incoming jitter exceeds either 120ui p - p (buffer depth is 128 bits) or 28ui p - p (buffer depth is 32 bit s), the ds26324 will divide the internal nominal 32.768mhz (e1) or 24.704mhz (t1) clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. when the device divides by either 15 or 17, it also sets the jitter attenuator limit tr ip (ijaflt) bits in the ijaflt register described. figure 5 - 9 . jitter attenuation frequency (hz) 0db -20db -40db -60db 1 10 100 1k 10k jitter attenuation (db) 100k tr 62411 (dec. 90) prohibited area curve b curve a itu g.7xx prohibited area tbr12 prohibited area t1 e1
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 32 of 120 5.7 g.772 monitor in this application, only 14 transceivers are functional and two t ransceivers are used for nonintrusive monitoring of input and output of the other 14 channels. channel 9 is used for 10 to 16 channels and channel 1 is used for 2 to 8 channels. g.772 monitoring is configured by the bert and g.772 monitoring control regist er ( bgmc ) (see table 6 -9 ). while monitoring, channel 1 can be configured in remote loopback and the monitored signal can be output on ttip1 and tring1. while monitoring, channel 9 can be configured in remote loopback and the monitored signal can be output on ttip9 and tring9. 5.8 loopbacks the ds26324 provides four loopbacks for diagnostic purposes: analog loopback, digital loopback, remote loopback, and dual loopback. dual l oopback is accomplished by turning on digital loopback and remote loopback at the same time. 5.8.1 analog loopback the analog output of the transmitter ttip and tring is looped back to rtip and rring of the receiver. data at rtip and rring is ignored in analog l oopback. this is shown in figure 5 -10 . figure 5 - 10 . analog loopback line driver h d b3/ b8zs e ncoder o ptional j itte r a ttenuator t ra n s m it d igital transm it analog tclk tpos tneg h d b 3/ b 8zs d ecoder o ptional j it te r a ttenuator r eceive d igital r eceive a nalog rclk rpos rneg rtip rring
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 33 of 120 5.8.2 digital loopback the transmit system data tpos, tneg, a nd tclk will be looped back to output on rclk, rpos, and rneg. the data input at tpos and tneg is output on ttip and tring. all ones can also be output when selected by the transmit all ones enable register ( taoe ). sign als at rtip and rring will be ignored. this loopback is conceptually shown in figure 5 -11 . figure 5 - 11 . digital loopback line driver h d b3/ b8zs e ncoder o ptional j itte r a ttenuator t ra n s m it d igital transm it analog tclk tpos tneg h d b 3/ b 8zs d ecoder o ptional j it te r a ttenuator r eceive d igital r eceive a nalog rclk rpos rneg rtip rring tpos tneg 5.8.3 r emote loopback the inputs at rtip and rring are looped back to ttip and tring. the inputs at tclk, tpos, and tneg are ignored during a remote loopback. this loopback is conceptually shown in figure 5 -12 . note: remote loopback does not take precedence over transmit power - down and requires tclk to operate. the transmitters will use the recovered rclk in remote loopback. tclk is still required because if it is removed the transmitters will power - down (tclk he ld low) or transmit all ones (tclk held high). figure 5 - 12 . remote loopback line driver h d b3/ b8zs e ncoder o ptional j itte r a ttenuator t ra n s m it d igital transm it analog tclk tpos tneg h d b 3/ b 8zs d ecoder o ptional j it te r a ttenuator r eceive d igital r eceive a nalog rclk rpos rneg rtip rring tpos tneg ttip tring ttip tring
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 34 of 120 5.9 bert there are two bit error - rate testers available on the ds26324. one bert can be mapped into l ius 1 ? 8 and the other into lius 9 ? 16 via the btcr registers. the two berts operate independently of each other. each bert transmitter, by default, replaces data from tpos and tneg; each bert receiver, by default, sample s recovered data from rtip and rring. the bert can be enabled to replace data received on rtip and rring via the bertdir bit in the bert and g.772 monitoring control register ( bgmc ). in this mode, the srms bit determine s whether data comes out single - rail or dual - rail. bert data can be sourced using the recovered clock, mclk, or tclk. in this mode of operation, the bert receiver samples data on tpos and tneg on the falling edge of tclk. this function is useful for testin g the digital side of the liu. if tclk is selected as a source for this mode, the input tclk will control the bert transmitter and receiver. if the recovered clock or mclk is selected, the rclk output needs to drive the tclk input in order for the bert rec eiver to sync to the data. 5.9.1 general description the bert is a software - programmable test pattern generator and monitor capable of meeting most error performance requirements for digital transmission equipment. it will generate and synchronize to pseudorando m patterns with a generation polynomial of the form x n + x y + 1, where n and y can take on values from 1 to 32 and repetitive patterns of any length up to 32 bits. the transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data stream. the receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern payload for the programmable test pattern. 5.9.1.1 bert features ? programmable prbs pattern. the pseudorandom bit seq uence (prbs) polynomial (x n + x y + 1) and seed are programmable (length n = 1 to 32, tap y = 1 to n ? 1, and seed = 0 to 2 n ? 1). ? programmable repetitive pattern. the repetitive pattern length and pattern are programmable (the length n = 1 to 32 and patter n = 0 to 2 n ? 1). ? 24- bit error count and 32- bit bit count registers ? programmable bit - error insertion. errors can be inserted individually, on a pin transition, or at a specific rate. the rate 1/10 n is programmable (n = 1 to 7). ? pattern synchronization at a 10 -3 ber. pattern synchronization is achieved even in the presence of a random bit error rate (ber) of 10 -3 .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 35 of 120 5.9.2 configuration and monitoring set btcr .berte = 1 to enable the bert. the following tables show how to configur e the on - board bert to send and receive common patterns. table 5 - 11 . pseudorandom pattern generation pattern type bpcr register bert. pcr bert. spr2 bert. spr1 bert.cr p tf[4:0] (hex) plf[4:0] (hex) pts qrss tpic, rpic 2 9 - 1 o.153 (511 type) 04 08 0 0 0x0408 0xffff 0xffff 0 2 11 - 1 o.152 and o.153 (2047 type) 08 0a 0 0 0x080a 0xffff 0xffff 0 2 15 - 1 o.151 0d 0e 0 0 0x0d0e 0xffff 0xffff 1 2 20 - 1 o.153 10 13 0 0 0x1013 0xff ff 0xffff 0 2 20 - 1 o.151 qrss 02 13 0 1 0x0253 0xffff 0xffff 0 2 23 - 1 o.151 11 16 0 0 0x1116 0xffff 0xffff 1 table 5 - 12 . repetitive pattern generation pattern type bpcr re gister bert. pcr bert. spr2 bert. spr1 ptf[4:0] (hex) plf[4:0] (hex) pts qrss all ones na 00 1 0 0x0020 0xffff 0xffff all zeros na 00 1 0 0x0020 0xffff 0xfffe alternating ones and zeros na 01 1 0 0x0021 0xffff 0xfffe double alternating and zeros n a 03 1 0 0x0023 0xffff 0xfffc 3 in 24 na 17 1 0 0x0037 0xff20 0x0022 1 in 16 na 0f 1 0 0x002f 0xffff 0x0001 1 in 8 na 07 1 0 0x0027 0xffff 0xff01 1 in 4 na 03 1 0 0x0023 0xffff 0xfff1 after configuring these bits, the pattern must be loaded into the bert. this is accomplished via a zero - to - one transition on bcr .tnpl and bcr .rnpl monitoring the bert requires reading the bsr register, which contains the bit error count (bec) bit and the out of synchronization (oos) bit. the bec bit will be one when the bit error counter is one or more. the oos will be one when the receive pattern generator is not synchronized to the incoming pattern, which will occur when it receives a minimum 6 bit errors within a 64 - bit window. the receive bert bit count register ( rbcr ) and the receive bert bit error count register ( rbecr ) will be updated upo n the reception of a performance monitor update signal (e.g., bcr . lpmu). this signal will update the registers with the values of the counters since the last update and will reset the counters.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 36 of 120 5.9.3 receive pattern detection t he receive bert receives only the payload data and synchronizes the receive pattern generator to the incoming pattern. the receive pattern generator is a 32 - bit shift register that shifts data from the least significant bit (lsb) or bit 1 to the most signi ficant bit (msb) or bit 32. the input to bit 1 is the feedback. for a prbs pattern (generating polynomial x n + x y + 1) , the feedback is an xor of bit n and bit y. for a repetitive pattern (length n), the feedback is bit n. the values for n and y are indivi dually programmable (1 to 32). the output of the receive pattern generator is the feedback. if qrss is enabled, the feedback is an xor of bits 17 and 20, and the output will be forced to one if the next 14 bits are all zeros. qrss is programmable (on or of f). for prbs and qrss patterns, the feedback will be forced to one if bits 1 through 31 are all zeros. depending on the type of pattern programmed, pattern detection performs either prbs synchronization or repetitive pattern synchronization. 5.9.3.1 receive prbs s ynchronization prbs synchronization synchronizes the receive pattern generator to the incoming prbs or qrss pattern. the receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and then checking the next 32 data stream bits. synchronization is achieved if all 32 bits match the incoming pattern. if at least six incoming bits in the current 64 - bit window do not match the receive pattern generator, automatic pattern re - synchronization is initiated. automatic pattern re - synchronization can be disabled. see figure 5 -13 for the prbs synchronization diagram. figure 5 - 13 . prbs synchronization state diagram sync load verify 1 bit error 32 bits loaded 32 bits without errors 6 of 64 bits with errors
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 37 of 120 5.9.3.2 receiv e repetitive pattern synchronization repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern. the receive pattern generator is synchronized by searching each incoming data stream bit position for the repetitive pattern, and then checking the next 32 data stream bits. synchronization is achieved if all 32 bits match the incoming pattern. if at least six incoming bits in the current 64 - bit window do not match the receive prbs pattern generator, automati c pattern re - synchronization is initiated. automatic pattern re- synchronization can be disabled. see figure 5 -14 for the repetitive pattern synchronization state diagram. figure 5 - 14 . repetitive pattern synchronization state diagram sync match verify 1 bit error pattern matches 32 bits without errors 6 of 64 bits with errors 5.9.3.3 receive pattern monitoring receive pattern monitoring monitors the incoming data stream for both an oos condition and bit errors and counts the incoming bits. an out of synchr onization (oos) condition is declared when the synchronization state machine is not in the ?sync? state. an oos condition is terminated when the synchronization state machine is in the ?sync? state. bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output. if they do not match, a bit error is declared, and the bit error and bit counts are incremented. if they match, only the bit count is incremented . the bit count and bit error count are not incremented whe n an oos condition exists .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 38 of 120 5.9.4 transmit pattern generation pattern generation generates the outgoing test pattern, and passes it onto error insertion. the transmit pattern generator is a 32 - bit shift register that shifts data from the least significant bit (ls b) or bit 1 to the most significant bit (msb) or bit 32. the input to bit 1 is the feedback. for a prbs pattern (generating polynomial x n + x y + 1) , the feedback is an xor of bit n and bit y. for a repetitive pattern (length n), the feedback is bit n. the values for n and y are individually programmable (1 to 32). the output of the receive pattern generator is the feedback. if qrss is enabled, the feedback is an xor of bits 17 and 20, and the output will be forced to one if the next 14 bits are all zeros. q rss is programmable (on or off). for prbs and qrss patterns, the feedback will be forced to one if bits 1 through 31 are all zeros. when a new pattern is loaded, the pattern generator is loaded with a seed/pattern value before pattern generation starts. th e seed/pattern value is programmable (0 ? 2 n ? 1). 5.9.4.1 transmit error insertion error insertion inserts errors into the outgoing pattern data stream. errors are inserted one at a time or at a rate of one out of every 10 n bits. the value of n is programmable (1 to 7 or off) . single bit error insertion can be initiated from the microprocessor interface, or by the manual error insertion input (tmei). the method of single error insertion is programmable (register or input). if pattern inversion is enabled, the data stream is inverted before the overhead/stuff bits are inserted. pattern inversion is programmable (on or off).
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 39 of 120 6 register maps and de finition six address bits are used to control the settings of the registers. in the parallel nonmultiplexed mode address [5: 0] is used. in multiplexed mode ad[5:0] is used and a[6:1] is used in the serial mode. the register space contains two independent sets of registers. the lower set of registers (lius 1 ? 8) is located from address 00 hex to 1f hex and contains controls for l ius 1 ? 8. the upper set of registers (lius 9 ? 16) is a duplicate of the lower set, located from address 20 hex to 3f hex that controls lius 9 ? 16. each of these sets of registers consists of four banks: primary, secondary, individual liu, and bert. the addp register for the lower set of registers (lius 1 ? 8) is located at address 1f hex. this register is used as a pointer to access the 4 banks of registers in the lower (lius 1 ? 8) register set. similarly, the addp register for the upper set of registers (lius 9 ? 16) is located at address 3f hex. this register is used as a pointer to access the four banks of registers in the upper (lius 9 ? 16) register set. setting an addp register to aa hex will access the secondary bank of registers, 01 hex will access the individual liu bank of registers, 02 hex will access the bert bank of registers, and 00 hex (default on power - up) will access the primary bank of regist ers. note that bank selection for the lower set of registers (lius 1 ? 8) is controlled only by the addp at 1f hex and that bank selection for the upper set of registers (lius 9 ? 16) is controlled only by the addp at 3f hex.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 40 of 120 table 6 - 1 . primary register set register name hex for ch 1 ? 8 address for ch 1 ? 8 hex for ch 9 ? 16 address for ch 9 ? 16 rw parallel interface a[7:0] (hex) serial interface a[7:1] (hex) parallel interface a[7:0] (hex) serial interface a[7:1] (hex) identification id 00 xx000000 x000000 20 not used not used r analog loopback control albc 01 xx000001 x000001 21 xx100001 x100001 rw remote loopback control rlbc 02 xx000010 x000010 22 xx100010 x100010 rw transmit all ones enable taoe 03 xx000011 x000011 23 xx100011 x100011 rw loss of signal status loss 04 xx000100 x 000100 24 xx100100 x100100 r driver fault monitor status dfms 05 xx000101 x000101 25 xx100101 x100101 r loss of signal interrupt enable losie 06 xx000110 x000110 26 xx100110 x100 110 rw driver fault monitor interrupt enable dfmie 07 xx000111 x000111 27 xx100111 x100111 rw loss of signal interrupt status losis 08 xx001000 x001000 28 xx101000 x101000 r driver fault monitor interrupt status dfmis 09 xx001001 x001001 29 xx101001 x101001 r software reset swr 0a xx001010 x001010 2a xx101010 x101010 w bert and g.772 monitoring control bgmc 0b xx001011 x001011 2b xx101011 x101011 rw digital loopback control dlbc 0c xx001100 x001100 2c xx101100 x101100 rw los/ais criteria selection lascs 0d xx001101 x001101 2d xx101101 x101101 rw automatic transmit all ones select ataos 0e xx001110 x001110 2e xx101110 x101110 rw global configuration gc 0f xx001111 x001 111 2f xx101111 x101111 rw template select transmitter tst 10 xx010000 x010000 30 xx110000 x110000 rw template select ts 11 xx010001 x010001 31 xx110001 x110001 rw output enable confi guration oe 12 xx010010 x010010 32 xx110010 x110010 rw alarm indication signal status ais 13 xx010011 x010011 33 xx110011 x110011 r ais interrupt enable aisie 14 xx010100 x010100 34 xx110100 x110100 rw ais interrupt status aisis 15 xx010101 x010101 35 xx110101 x110101 r reserved ? 16? 1e xx010110 ? xx011110 x010110 ? x011110 36? 3e xx110110 ? x111110 x110110 ? x111110 ? address pointer for bank selection addp 1f xx011111 x011111 3f xx111111 x111111 rw
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 41 of 120 table 6 - 2 . secondary register set register name hex for ch 1 ? 8 address for channels 1 ? 8 hex for ch 9 ? 16 address for channels 9 ? 16 rw parallel interface a[7:0] (hex) serial interface a[7:1] (hex) parallel interface a[7:0] (hex) serial interface a[7:1] (hex) single - rail mode select srms 00 xx00000 0 x000000 20 xx100000 x100000 rw line code selection lcs 01 xx000001 x000001 21 xx100001 x100001 r not used ? 02 xx000010 x000010 22 xx100010 x100010 r receive power - down enable rpde 03 xx000011 x000011 23 xx100011 x100011 rw transmit power - down enable tpde 04 xx000100 x000100 24 xx100100 x100100 rw excessive zero detect enable ezde 05 xx000101 x000101 25 xx1 00101 x100101 r code violation detect enable bar cvdeb 06 xx000110 x000110 26 xx100110 x100110 r not used ? 07? 1e xx000111 ? xx011110 x000111 ? x011110 27? 3e xx100111 ? xx111110 x100111 ? x111110 w address pointer for bank selection addp 1f xx011111 x011111 3f xx111111 x111111 rw
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 42 of 120 table 6 - 3 . individual liu register set register name hex for ch 1 ? 8 address for channels 1 ? 8 hex for ch 9 ? 16 a ddress for channels 9 ? 16 rw parallel interface a[7:0] (hex) serial interface a[7:1] (hex) parallel interface a[7:0] (hex) serial interface a[7:1] (hex) individual jitter attenuator enable ijae 00 xx000000 x000000 20 xx100000 x100000 rw individual jitter attenuator position select ijaps 01 xx000001 x000001 21 xx100001 x100001 rw individual jitter attenuator fifo depth select ijafds 02 xx000010 x000010 22 xx100010 x100010 rw individual jitter attenuator fifo limit trip ijaflt 03 xx000011 x000011 23 xx100011 x100011 r individual short - circuit protection disable i scpd 04 xx000100 x000100 24 xx100100 x100100 rw individual ais select iaisel 05 xx000101 x000101 25 xx100101 x100101 rw master clock select mc 06 xx000110 x000110 26 not used not used rw receive sensitivity monitor mode 1 ? 4 rsmm1 , rsmm2 , rsmm3 , rsmm4 08? 0b xx001000 ? xx001011 x001000 ? x001011 28? 2b xx101000 ? xx101011 x101000 ? x101011 rw receive signal level indicator 1 ? 4 rsl 1 ? 4 0c? 0f xx001100 ? xx001111 x001100 ? x001111 2c? 2f xx101100 ? xx101111 x101100 ? x101111 r bit error rate tester control btcr 10 xx010000 x010000 30 xx110000 x110000 rw line violation detect status lvds 12 xx010010 x010010 32 xx110010 x110010 r receive clock invert rclki 13 xx010011 x010011 33 xx110011 x110011 rw transmit clock invert tclki 14 xx010100 x010100 34 xx110100 x110100 rw clock control register ccr 15 xx010101 x010101 35 not used no t used rw rclk disable upon los rdulr 16 xx010110 x010110 36 xx110110 x110110 rw global interrupt status control gisc 1e xx011110 x011110 3e not used not used rw address pointe r for bank selection addp 1f xx011111 x011111 3f xx111111 x111111 rw
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 43 of 120 table 6 - 4 . bert register set register name hex for ch 1 ? 8 address for channels 1 ? 8 hex for ch 9 ? 16 a ddress for channels 9 ? 16 rw parallel interface a[7:0] (hex) serial interface a[7:1] (hex) parallel interface a[7:0] (hex) serial interface a[7:1] (hex) bert control bcr 00 xx000000 x000000 20 xx100000 x100000 rw reserved ? 01 xx000001 x000001 21 xx100001 x100001 ? bert pattern configuration 1 bpcr1 02 xx000010 x000010 22 xx100010 x100010 rw bert pattern configuration 2 bpcr2 03 xx00001 1 x000011 23 xx100011 x100011 rw bert seed/pattern 1 bspr1 04 xx000100 x000100 24 xx100100 x100100 rw bert seed/pattern 2 bspr2 05 xx000101 x000101 25 xx100101 x100101 rw bert seed/pattern 3 bspr3 06 xx000110 x000110 26 xx100110 x100110 rw bert seed/pattern 4 bspr4 07 xx000111 x000111 27 xx100111 x100111 rw transmit error insertion control teicr 08 xx001000 x001000 28 xx101000 x101000 rw reserved ? 09? 0a xx001001 ? x001010 ? 29? 2a xx101001 ? x101010 ? ? bert status bsr 0c xx001100 x001100 2c xx101100 x101100 r reserved ? 0d xx0 01101 x001101 2d xx101101 x101101 ? bert status register latched bsrl 0e xx010011 x010011 2e xx110011 x110011 rw bert status register interrupt enable bsrie 10 xx010000 x010000 30 xx110000 x110000 rw reserved ? 11? 13 xx010001 ? xx010011 x010001 ? x010011 31? 33 xx110001 ? xx110011 x110001 ? x110011 ? receive bit error count register 1 rbecr1 14 xx010100 x010100 34 xx110100 x110100 r receive bit error count register 2 rbecr2 15 xx010101 x010101 35 xx110101 x110101 r receive bit error count register 3 rbecr3 16 xx010110 x010110 36 xx110110 x110110 r receive bit coun t register 1 rbcr1 18 xx011000 x011000 38 xx111000 x111000 r receive bit count register 2 rbcr2 19 xx011001 x011001 39 xx111001 x111001 r receive bit count register 3 rbcr3 1a xx011010 x011010 3a xx111010 x111010 r receive bit count register 4 rbcr4 1b xx011011 x011011 3b xx111011 x111011 r reserved ? 1c? 1e xx011100 ? xx011110 x011100 ? x011110 3c? 3e x x111100 ? xx111110 x111100 ? x111110 ? address pointer for bank selection addp 1f xx011111 x011111 3f xx111111 x111111 rw
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 44 of 120 table 6 - 5 . primary register set bit map register ad dress for lius 1 ? 8 r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 id 00 r id7 id6 id5 id4 id3 id2 id1 id0 albc 01 rw albc8 albc7 albc6 albc5 albc4 albc3 albc2 albc1 rlbc 02 rw rlbc8 rlbc7 rlbc6 rlbc5 rlbc4 rlbc3 rlbc2 rlbc1 taoe 03 rw taoe8 taoe7 taoe6 taoe5 taoe4 taoe3 taoe2 taoe1 loss 04 rw loss8 loss7 loss6 loss5 los s4 loss3 loss2 loss1 dfms 05 rw dfms8 dfms7 dfms6 dfms5 dfms4 dfms3 dfms2 dfms1 losie 06 rw losie8 losie7 losie6 losie5 losie4 losie3 losie2 losie1 dfmie 07 rw dfmie8 dfmie7 dfmie6 dfmie5 dfmie4 dfmie3 dfmie2 dfmie1 losis 08 r losis8 losis7 losis6 losis5 losis4 losis3 losis2 losis1 dfmis 09 r dfmis8 dfmis7 dfmis6 dfmis5 dfmis4 dfmis3 dfmis2 dfmis1 sw r 0a w sw rl sw rl sw rl sw rl sw rl sw rl sw rl sw rl bgmc 0b rw bertdir bmcks btcks ? gmc4 gmc3 gmc2 gmc1 dlbc 0 c rw dlbc8 dlbc7 dlbc6 dlbc5 dlbc4 dlbc3 dlbc2 dlbc1 lascs 0d rw lascs8 lascs7 lascs6 lascs5 lascs4 lascs3 lascs2 lascs1 ataos 0e rw ataos8 ataos7 ataos6 ataos5 ataos4 ataos3 a taos2 ataos1 gc 0f rw rimpms aisel scpd code jads crimp japs jae tst 10 rw jabws1 jabws0 rhpmc ? ? tst2 tst1 tst0 ts 11 rw rimpon timpoff ? ? timprm ts2 ts1 ts0 oe 12 rw oe8 oe7 oe6 oe5 oe4 oe3 oe2 oe1 ais 13 r ais8 ais7 ais6 ais5 ais4 ais3 ais2 ais1 aisie 14 rw aisie8 aisie7 aisie6 aisie5 aisie4 aisie3 aisie2 aisie1 aisis 15 r aisis8 aisis7 aisis6 aisis5 aisis4 aisis3 aisis2 aisis1 not used 16 - 1e ? ? ? ? ? ? ? ? ? addp 1f rw addp7 addp6 addp5 addp4 addp3 addp2 addp1 add p0 register address for lius 9 ? 16 r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 not used 20 r ? ? ? ? ? ? ? ? albc 21 rw alc16 albc15 albc14 albc13 albc12 albc11 albc10 albc9 r lbc 22 rw rlbc16 rlbc15 rlbc14 rlbc13 rlbc12 rlbc11 rlbc10 rlbc9 taoe 23 rw taoe16 taoe15 taoe14 taoe13 taoe12 taoe11 taoe10 taoe9 loss 24 rw loss16 loss15 loss14 loss13 loss1 2 loss11 loss10 loss9 dfms 25 rw dfms16 dfms15 dfms14 dfms13 dfms12 dfms11 dfms10 dfms9 losie 26 rw losie16 losie15 losie14 losie13 losie12 losie11 losie10 losie9 dfmie 27 rw dfmie16 dfmie15 dfmie14 dfmie13 dfmie12 dfmie11 dfmie10 dfmie9 losis 28 r losis16 losis15 losis14 losis13 losis12 losis11 losis10 losis9 dfmis 29 r dfmis16 dfmis15 dfmis14 dfmis13 dfmis12 dfmis11 dfmis10 dfmis9 sw r 2a w sw ru sw ru sw ru sw ru sw ru sw ru sw ru sw ru bgmc 2b rw bertdir bmcks btcks ? gmc4 gmc3 gmc2 gmc1 dlbc 2c rw dlbc16 dlbc15 dlbc14 dlbc13 dlbc12 dlbc11 dlbc10 dlbc9 lascs 2d rw lascs16 lascs15 lascs14 lascs13 lascs12 lascs11 lascs10 lascs9 ataos 2e rw ataos16 ataos15 ataos14 ataos13 ataos12 ataos11 ataos10 ataos9 gc 2f rw rimpms aisel scpd code jads calen japs jae tst 30 rw ? ? ? ? ? tst2 tst1 tst0 ts 31 rw rimpon timpoff ? ? timprm ts2 ts1 ts0 oe 32 rw oe16 oe15 oe14 oe13 oe12 oe11 oe10 oe9 ais 33 r ais16 ais15 ais14 ais13 ais12 ais11 ais10 ais9 aisie 34 rw aisie16 aisie15 aisie14 aisie13 aisie12 aisie11 aisie10 aisie9 aisis 35 r aisis16 aisis15 aisis14 aisis13 aisis12 aisis11 aisis10 aisis9 not used 36 - 3e ? ? ? ? ? ? ? ? ? addp 3f rw addp7 addp6 addp5 addp4 addp3 addp2 addp1 addp0 note: underlined bits are read only.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 45 of 120 table 6 - 6 . secondary register set bit map register address for lius 1 ? 8 rw bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 srms 00 rw srms8 srms7 srms6 srms5 srms4 srms3 srms2 srms1 lcs 01 rw lcs8 lcs7 lcs6 lcs5 lsc4 lcs3 lsc2 lsc1 not used 02 rw ? ? ? ? ? ? ? ? rpde 03 rw rpde8 rpde7 rpde6 rpde5 rpde4 rpde3 rpde2 rpde1 tpde 04 rw tpde8 tdpe7 tpde6 tpde5 tpde4 tpde3 tpde2 tpde1 ezde 05 rw ezde8 ezde7 ezde6 ezde5 ezde 4 ezde3 ezde2 ezde1 cvdeb 06 rw cvdeb8 cvdeb7 cvdeb6 cvdeb5 cvdeb4 cvdeb3 cvdeb2 cvdeb1 not used 07 ? 1e ? ? ? ? ? ? ? ? ? addp 1f rw addp7 addp6 addp5 addp4 addp3 addp2 addp1 add p0 register address for lius 9 ? 16 rw bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 srms 20 rw srms16 srms15 srms14 srms13 srms12 srms11 srms10 srms9 lcs 21 rw lcs16 lcs15 lcs14 l cs13 lsc12 lcs11 lsc10 lsc9 not used 22 rw ? ? ? ? ? ? ? ? rpde 23 rw rpde16 rpde15 rpde14 rpde13 rpde12 rpde11 rpde10 rpde9 tpde 24 rw tpde16 tdpe15 tpde14 tpde13 tpde12 tpde11 t pde10 tpde9 ezde 25 rw ezde16 ezde15 ezde14 ezde13 ezde12 ezde11 ezde10 ezde9 cvdeb 26 rw cvdeb16 cvdeb15 cvdeb14 cvdeb13 cvdeb12 cvdeb11 cvdeb10 cvdeb9 not used 27 ? 3e ? ? ? ? ? ? ? ? ? addp 3f rw addp7 addp6 addp5 addp4 addp3 addp2 addp1 addp0
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 46 of 120 table 6 - 7 . individual liu register set bit map register address for lius 1 ? 8 rw bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ijae 00 rw ijae8 ijae7 ijae6 ijae5 ijae4 ijae3 ijae2 ijae1 ijaps 01 rw ijaps8 ijaps7 ijaps6 ijaps5 ijaps4 ijaps3 ijaps2 ijaps1 ijafds 02 rw ijafds8 ijafds7 ijafds6 ijafds5 ijafds4 ijafds3 ijafds2 ijafds1 ijaflt 03 r ijaflt8 ijaflt7 ijaflt6 ijaflt5 ijaflt4 ijaflt3 ijaflt2 ijaflt1 iscpd 04 rw iscpd8 iscpd7 iscpd6 iscpd5 iscpd4 iscpd3 iscpd2 iscpd1 iaisel 05 rw iaisel8 iaisel7 iaisel6 iaisel5 iaisel4 iaisel3 iaisel2 iaisel1 mc 06 rw pclki1 pclki0 teclke clkae mp s1 mps0 freqs plle rsmm1 08 rw rtr2 c2rsm2 c2rsm1 c2rsm0 rtr1 c1rsm2 c1rsm1 c1rsm0 rsmm2 09 rw rtr4 c4rsm2 c4rsm1 c4rsm0 rtr3 c3rsm2 c3rsm1 c3rsm0 rsmm3 0a rw rtr6 c6rsm2 c6rsm1 c6rsm0 rtr5 c5rsm2 c5rsm1 c5rsm0 rsmm4 0b rw rtr8 c8rsm2 c8rsm1 c8rsm0 rtr7 c7rsm2 c7rsm1 c7rsm0 rsl1 0c r c2rsl3 c2rsl2 c2rsl1 c2rsl0 c1 rsl3 c1rsl2 c1rsl1 c1rsl0 rsl2 0d r c4rsl3 c4rsl2 c4rsl1 c4rsl0 c3rsl3 c3rsl2 c3rsl1 c3rsl0 rsl3 0e r c6rsl3 c6rsl2 c6rsl1 c6rsl0 c5rsl3 c5rsl2 c5rsl1 c5rsl0 rsl4 0f r c8rsl3 c8rsl2 c8rsl1 c8rsl0/ calstat c7rsl3 c7rsl2 c7rsl1 c7rsl0 btcr 10 rw bts2 bts1 bts0 ? ? ? ? berte beir 11 rw beir8 beir7 beir6 beir5 beir4 beir3 bei r2 beir1 lvds 12 r lvds8 lvds7 lvds6 lvds5 lvds4 lvds3 lvds2 lvds1 rclki 13 rw rclki8 rclki7 rclki6 rclki5 rclki4 rclki3 rclki2 rclki1 tclki 14 rw tclki8 tclki7 tclki6 tclki5 tclki4 tclki3 tclki2 tclki1 ccr 15 rw pclks2 pclks1 pclks0 teclks clka3 clka2 clka1 clka0 rdulr 16 rw rdulr8 rdulr7 rdulr6 rdulr5 rdulr4 rdulr3 rdulr2 rdulr1 gisc 1e rw ? ? ? ? ? ? intm cw e addp 1f rw addp7 addp6 addp5 addp4 addp3 addp2 addp1 addp0 register address for lius 9 ? 16 rw bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bi t 1 bit 0 ijae 20 rw ijae16 ijae15 ijae14 ijae13 ijae12 ijae11 ijae10 ijae9 ijaps 21 rw ijaps16 ijaps15 ijaps14 ijaps13 ijaps12 ijaps11 ijaps10 ijaps9 ijafds 22 rw ijafds16 ijafds15 ijafds14 ijafds13 ijafds12 ijafds11 ijafds10 ijafds9 ijaflt 23 r ijaflt16 ijaflt15 ijaflt14 ijaflt13 ijaflt12 ijaflt11 ijaflt10 ijaflt9 iscpd 24 rw iscpd16 iscpd15 iscpd14 iscpd13 iscpd12 iscpd11 iscpd10 iscpd9 iaisel 25 rw iaisel16 iaisel15 iaisel14 iaisel13 iaisel12 iaisel11 iaisel10 iaisel9 not used 26 rw ? ? ? ? ? ? ? ? rsmm1 28 rw rtr10 c10rsm2 c10rsm1 c10rsm0 rtr9 c9rsm2 c9rsm1 c9rsm0 rsmm2 29 rw rtr12 c12rsm2 c12rsm1 c12rsm0 rtr11 c11rsm2 c11rsm1 c11rsm0 rsmm3 2a rw rtr14 c14rsm2 c14rsm1 c14rsm0 rtr13 c13rsm2 c13rsm1 c13rsm0 rsmm4 2b rw rtr16 c16rsm2 c16rsm1 c16rsm0 rtr15 c15rsm2 c15rsm1 c15rsm0 rsl1 2c r c10rsl3 c10rsl2 c10rsl1 c10rsl0 c9rs l3 c9rsl2 c9rsl1 c9rsl0 rsl2 2d r c12rsl3 c12rsl2 c12rsl1 c12rsl0 c11rsl3 c11rsl2 c11rsl1 c11rsl0 rsl3 2e r c14rsl3 c14rsl2 c14rsl1 c14rsl0 c13rsl3 c13rsl2 c13rsl1 c13rsl0 rsl4 2f r c16rsl3 c16rsl2 c16rsl1 c16rsl0 c15rsl3 c15rsl2 c15rsl1 c15rsl0 btcr 30 rw bts2 bts1 bts0 ? ? ? ? berte beir 31 rw beir16 beir15 beir14 beir 13 beir12 beir11 beir10 beir9 lvds 32 r lvds16 lvds15 lvds14 lvds13 lvds12 lvds11 lvds10 lvds9 rclki 33 rw rclki16 rclki15 rclki14 rclki13 rclki12 rclki11 rclki10 rclki9 tclki 34 rw tclki16 tclki15 tclki14 tclki13 tclki12 tclki11 tclki10 tclki9 not used 35 rw ? ? ? ? ? ? ? ? rdulr 36 rw rdulr16 rdulr15 rdulr14 rdulr13 rdulr12 rdulr11 rdulr10 rdulr9 n ot used 3e rw ? ? ? ? ? ? intm cw e addp 3f rw addp7 addp6 addp5 addp4 addp3 addp2 addp1 addp0 note: underlined bits are read only.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 47 of 120 table 6 - 8 . bert register bit map regist er address for lius rw bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 ? 8 9 ? 16 bcr 00 20 rw pmum lpmu rnpl rpic mpr aprd tnpl tpic not used 01 21 ? ? ? ? ? ? ? ? ? bpcr1 02 22 rw ? qrss pts plf4 plf3 plf2 plf1 plf0 bpcr2 03 23 ? ? ? ? ptf4 ptf3 ptf2 ptf1 ptf0 bspr1 04 24 rw bsp7 bsp6 bsp5 bsp4 bsp3 bsp2 bsp1 bsp0 bspr2 05 25 ? bsp15 bsp14 bsp13 bsp12 bsp11 bsp10 bsp9 bsp8 bspr3 06 26 rw bsp23 bsp22 bsp21 bsp20 bsp19 bsp18 bsp17 bsp16 bspr4 07 27 ? bsp31 bsp30 bsp29 bsp28 bsp27 bsp26 bsp25 bsp24 teicr 08 28 rw ? ? teir2 teir1 teir0 bei tsei meims not used 09 ? 0b 29 ? 2b ? ? ? ? ? ? ? ? ? bsr 0c 2c r ? ? ? ? pms ? bec oos not used 0d 2d ? ? ? ? ? ? ? ? ? bsrl 0e 2e r ? ? ? ? pmsl bel becl oosl not used 0f 2f ? ? ? ? ? ? ? ? ? bsrie 10 30 rw ? ? ? ? pmsie beie becie oosie not used 11 ? 13 31 ? 33 ? ? ? ? ? ? ? ? ? rbecr1 14 34 r bec7 bec6 bec5 bec4 bec3 bec2 bec1 bec0 rbecr2 15 35 r bec15 bec14 bec13 bec12 bec11 bec10 bec9 bec8 rbecr3 16 36 r bec23 bec22 bec2 1 bec20 bec19 bec18 bec17 bec16 not used 17 37 ? ? ? ? ? ? ? ? ? rbcr1 18 38 r bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 rbcr2 19 39 r bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 rbcr3 1a 3a r bc23 bc22 bc21 bc20 bc19 bc18 bc17 bc16 rbcr4 1b 3b r bc31 bc30 bc29 bc28 bc27 bc26 bc25 bc24 not used 1c ? 1e 3c ? 3e ? ? ? ? ? ? ? ? ? addp 1f 3f rw addp7 addp6 addp5 addp4 addp3 addp2 addp1 addp0 note: underlined bits are read only.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 48 of 120 6.1 register description this section contains the detailed register descriptions of each bit. whenever the variable ? n ? in italics is used in any of the regis ter descriptions, it represents 1 ? 16. note that in the register descriptions, there are duplicate registers for lius 1 ? 8 and lius 9 ? 16. there are registers in lius 1 ? 8 that do not have a duplicate in the register set for lius 9 ? 16. for these registers, onl y one address is listed. all other registers list two addresses, one for lius 1 ? 8 and one for lius 9 ? 16. 6.1.1 primary register bank the addp register must be set to 00h to access this bank. register name: id register description: id register register addr ess: 00h bit # 7 6 5 4 3 2 1 0 name id7 id6 id5 id4 id3 id2 id1 id0 bit 7: device code id bit 7 (id7). this bit is ?zero? for short - haul operation. bits 6 to 3: device code id bits 6 to 3 (id6 to id3). these bits tell the user the number of ports th e device contains. bits 2 to 0: device code id bits 2 to 0 (id2 to id0). these bits tell the user the revision of the part. contact the factory for details. register name: albc register description: analog loopback control register address (lius 1 ? 8) : 01h bit # 7 6 5 4 3 2 1 0 name albc8 albc7 albc6 albc5 albc4 albc3 albc2 albc1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 21h bit # 7 6 5 4 3 2 1 0 name albc16 albc15 albc14 albc13 albc12 albc11 albc10 albc9 default 0 0 0 0 0 0 0 0 bits 7 to 0: analog loopback control bits channel n (albc n ). when this bit is set, liu n is placed in analog loopback. ttip and tring are looped back to rtip and rring. the data at rtip and rring is ignored. los detector is still in operation. the jitter attenuator is in use if enabled for the transmitter or receiver.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 49 of 120 register name: rlbc register description: remote loopback control register address (lius 1 ? 8): 02h bit # 7 6 5 4 3 2 1 0 name rlbc8 rlbc7 rlbc6 rlbc5 rlbc4 rlbc3 rlbc2 rlbc1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 22h bit # 7 6 5 4 3 2 1 0 name rlbc16 rlbc15 rlbc14 rlbc13 rlbc12 rlbc11 rlbc10 rlbc9 default 0 0 0 0 0 0 0 0 bits 7 to 0: remote loopback control bits channel n (rlbc n ). when this bit is set, remote lo opback is enabled on liu n . the analog received signal goes through the receive digital and is looped back to the transmitter. the data at tpos and tneg is ignored. the jitter attenuator is in use if enabled. register name: taoe register description: tr ansmit all ones enable register address (lius 1 ? 8): 03h bit # 7 6 5 4 3 2 1 0 name taoe8 taoe7 taoe6 taoe5 taoe4 taoe3 taoe2 taoe1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 23h bit # 7 6 5 4 3 2 1 0 name taoe16 taoe15 taoe14 taoe13 ta oe12 taoe11 taoe10 taoe9 default 0 0 0 0 0 0 0 0 bits 7 to 0: transmit all ones enable channel n (taoe n ). when this bit is set, continuous stream of all ones on ttip and tring are sent on channel n . mclk is used as a reference clock for transmit all one s signal. the data arriving at tpos and tneg is ignored. register name: loss register description: loss of signal status register address (lius 1 ? 8): 04h bit # 7 6 5 4 3 2 1 0 name loss8 loss7 loss6 loss5 loss4 loss3 loss2 loss1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 24h bit # 7 6 5 4 3 2 1 0 name loss16 loss15 loss14 loss13 loss12 loss11 loss10 loss9 default 0 0 0 0 0 0 0 0 bits 7 to 0: loss of signal status channel n (loss n ). when this bit is set, a los condition has been de tected on liu n . the criteria and conditions of los are described in section 5.5.6 .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 50 of 120 register name: dfms register description: driver fault monitor status register address (lius 1 ? 8): 05h bit # 7 6 5 4 3 2 1 0 name dfms8 dfms7 dfms6 dfms5 dfms4 dfms3 dfms2 dfms1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 25h bit # 7 6 5 4 3 2 1 0 name dfms16 dfms15 dfms14 dfms13 dfms12 dfms11 dfms10 dfms9 default 0 0 0 0 0 0 0 0 bits 7 to 0: driver fault mo nitor status channel n (dfms n ). when this bit is set, it indicates that there is a short or open circuit at the transmit driver for liu n . register name: losie register description: loss of signal interrupt enable register address (lius 1 ? 8): 06h bit # 7 6 5 4 3 2 1 0 name losie8 losie7 losie6 losie5 losie4 losie3 losie2 losie1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 26h bit # 7 6 5 4 3 2 1 0 name losie16 losie15 losie14 losie13 losie12 losie11 losie10 losie9 default 0 0 0 0 0 0 0 0 bits 7 to 0: loss of signal interrupt enable channel n (losie n ). when this bit is set, a change in los status for liu n can generate an interrupt. register name: dfmie register description: driver fault monitor interrupt enable register address (li us 1 ? 8): 07h bit # 7 6 5 4 3 2 1 0 name dfmie8 dfmie7 dfmie6 dfmie5 dfmie4 dfmie3 dfmie2 dfmie1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 27h bit # 7 6 5 4 3 2 1 0 name dfmie16 dfmie15 dfmie14 dfmie13 dfmie12 dfmie11 dfmie10 dfmie9 de fault 0 0 0 0 0 0 0 0 bits 7 to 0: driver fault monitor interrupt enable channel n (dfmie n ). when this bit is set, a change in dfm status can generate an interrupt in monitor n .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 51 of 120 register name: losis register description: loss of signal interrupt statu s register address (lius 1 ? 8): 08h bit # 7 6 5 4 3 2 1 0 name losis8 losis7 losis6 losis5 losis4 losis3 losis2 losis1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 28h bit # 7 6 5 4 3 2 1 0 name losis16 losis15 losis14 losis13 losis12 los is11 losis10 losis9 default 0 0 0 0 0 0 0 0 bits 7 to 0: loss of signal interrupt status channel n (losis n ). when this bit is set, it indicates a los status has transition from a ?0 to 1? or ?1 to 0? and was detected for liu n . the bit for liu n is enable d by register losie (06h). this bit when latched is cleared on a read operation. register name: dfmis register description: driver fault monitor interrupt status register address (lius 1 ? 8): 09h bit # 7 6 5 4 3 2 1 0 name dfmis8 dfmis7 dfmis6 dfmis5 dfmis4 dfmis3 dfmis2 dfmis1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 29h bit # 7 6 5 4 3 2 1 0 name dfmis16 dfmis15 dfmis14 dfmis13 dfmis12 dfmis11 dfmis10 dfmis9 default 0 0 0 0 0 0 0 0 bits 7 to 0: driver fault status register chan nel n (dfmis n ). when this bit is set, it indicates a dfm status has transitioned from ?0 to 1? or ?1 to 0? and was detected for liu n . the bit for liu n is enabled by register dfmie (07h). this bit when latched is cleared on a read operation.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 52 of 120 register name : swr register description: software reset register address (lius 1 ? 8): 0ah bit # 7 6 5 4 3 2 1 0 name swrl swrl swrl swrl swrl swrl swrl swrl default 0 0 0 0 0 0 0 0 bits 7 to 0: software reset (swrl). whenever any write is performed to this regi ster, at least 1 s reset will be generated that resets the lower set of registers (lius 1 ? 8). all the registers will be restored to their default values. a read operation will always read back all zeros. register address (lius 9 ? 16): 2ah bit # 7 6 5 4 3 2 1 0 name swru swru swru swru swru swru swru swru default 0 0 0 0 0 0 0 0 bits 7 to 0: software reset (swru). whenever any write is performed to this register, at least 1 s reset will be generated that resets the upper set of registers (lius 9 ? 16). a ll the registers will be restored to their default values. a read operation will always read back all zeros.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 53 of 120 register name: bgmc register description: bert and g.772 monitoring control register address (lius 1 ? 8): 0bh bit # 7 6 5 4 3 2 1 0 name bert dir bmcks btcks ? gmc3 gmc2 gmc1 gmc0 default 0 0 0 0 0 0 0 0 bit 7: bert direction control bit (bertdir). when this bit is set, the bert for lius 1 ? 8 will be enabled on the system side of the part (bert data will come out on rpos/rneg and be expected o n tpos/tneg) for whichever liu the bert is enabled. bit 6: bert mclk selection (bmcks). when the bert is enabled on the system side (bertdir = 1), setting this bit will select mclk as the bert clock unless btcks is set. if neither bmcks nor btcks is set, t he bert will use the recovered clock. bit 5: bert tclk selection (btcks). when the bert is enabled on the system side (bertdir = 1), setting this bit selects tclk as the bert clock, regardless of the state of the bmcks bit. if neither bmcks nor btcks is s et, the bert will use the recovered clock. bits 3 to 0: g.772 monitoring control (gmc[3:0]). these bits are used to select transmitter or receiver for nonintrusive monitoring. receiver 1 is used to monitor channels 2 to 8 of one receiver from rtip2 ? rtip8/r ring2 ? rring8 or of one transmitter from ttip2 ? ttip8/tring2 ? tring8. see table 6 -9 . register address (lius 9 ? 16): 2bh bit # 7 6 5 4 3 2 1 0 name bertdir bmcks btcks ? gmc3 gmc2 gmc1 gmc0 default 0 0 0 0 0 0 0 0 bit 7: bert direction control bit (bertdir). when this bit is set, the bert for lius 9 ? 16 will be enabled on the system side of the part (bert data will come out on rpos/rneg and be expected on tpos/tneg) for whichever liu the bert is enabled. bi t 6: bert mclk selection (bmcks). when the bert is enabled on the system side (bertdir = 1), setting this bit will select mclk as the bert clock unless btcks is set. if neither bmcks nor btcks is set, the bert will use the recovered clock. if the clock use d as the bert clock is mclk or the recovered clock, tclk must be frequency locked to the bert clock in order for the bert to sync. bit 5: bert tclk selection (btcks). when the bert is enabled on the system side (bertdir = 1), setting this bit selects tclk as the bert clock, regardless of the state of the bmcks bit. if neither bmcks nor btcks is set, the bert will use the recovered clock. bits 3 to 0: g.772 monitoring control (gmc) . these bits are used to select transmitter or receiver for nonintrusive monit oring. receiver 9 is used to monitor channels 10 to 16 of one receiver from rtip10 ? rtip16/rring10 ? rring16 or of one transmitter from ttip10 ? ttip16/tring10 ? tring16. see table 6 -10 .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 54 of 120 table 6 - 9 . g.772 monitoring control (liu 1) gmc3 gmc2 gmc1 gmc0 selection 0 0 0 0 no monitoring 0 0 0 1 receiver 2 0 0 1 0 receiver 3 0 0 1 1 receiver 4 0 1 0 0 receiver 5 0 1 0 1 receiver 6 0 1 1 0 receiver 7 0 1 1 1 receive r 8 1 0 0 0 no monitoring 1 0 0 1 transmitter 2 1 0 1 0 transmitter 3 1 0 1 1 transmitter 4 1 1 0 0 transmitter 5 1 1 0 1 transmitter 6 1 1 1 0 transmitter 7 1 1 1 1 transmitter 8 table 6 - 10 . g.772 mo nitoring control (liu 9) gmc3 gmc2 gmc1 gmc0 selection 0 0 0 0 no monitoring 0 0 0 1 receiver 10 0 0 1 0 receiver 11 0 0 1 1 receiver 12 0 1 0 0 receiver 13 0 1 0 1 receiver 14 0 1 1 0 receiver 15 0 1 1 1 receiver 16 1 0 0 0 no monitoring 1 0 0 1 transmitter 10 1 0 1 0 transmitter 11 1 0 1 1 transmitter 12 1 1 0 0 transmitter 13 1 1 0 1 transmitter 14 1 1 1 0 transmitter 15 1 1 1 1 transmitter 16
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 55 of 120 register name: dlbc register description: digital loopback control register address (lius 1 ? 8): 0ch bit # 7 6 5 4 3 2 1 0 name dlbc8 dlbc7 dlbc6 dlbc5 dlbc4 dlbc3 dlbc2 dlbc1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 2ch bit # 7 6 5 4 3 2 1 0 name dlbc16 dlbc15 dlbc14 dlbc13 dlbc12 dlbc11 dlbc10 dlbc9 default 0 0 0 0 0 0 0 0 bits 7 to 0: digital loopback control channel n (dlbc n ). when this bit is set the liu n is placed in digital loopback. the data at tpos/tneg is encoded and looped back to the decoder and output on rpos/rneg. the jitter attenuator can optionally be incl uded in the transmit or receive paths. register name: lascs register description: los/ais criteria selection register address (lius 1 ? 8): 0dh bit # 7 6 5 4 3 2 1 0 name lascs8 lascs7 lascs6 lascs5 lascs4 lascs3 lascs2 lascs1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 2dh bit # 7 6 5 4 3 2 1 0 name lascs16 lascs15 lascs14 lascs13 lascs12 lascs11 lascs10 lascs9 default 0 0 0 0 0 0 0 0 bits 7 to 0: los/ais criteria selection channel n (lascs n ). this bit is used for los/ais selectio n criteria for liu n . in e1 mode, if set it uses ets 300 233 mode selections. if reset it uses g.775 criteria. in t1/j1 mode t1.231 criteria is selected. register name: ataos register description: automatic transmit all ones select register address (liu s 1 ? 8): 0eh bit # 7 6 5 4 3 2 1 0 name ataos8 ataos7 ataos6 ataos5 ataos4 ataos3 ataos2 ataos1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 2eh bit # 7 6 5 4 3 2 1 0 name ataos16 ataos15 ataos14 ataos13 ataos12 ataos11 ataos10 ataos9 d efault 0 0 0 0 0 0 0 0 bits 7 to 0: automatic transmit all ones select channel n (ataos n ). when this bit is set all ones signal is sent if an los is detected for liu n . ?all ones signal? uses mclk as the reference clock.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 56 of 120 register name: gc register descri ption: global configuration register address (lius 1 ? 8): 0fh bit # 7 6 5 4 3 2 1 0 name rimpms aisel scpd code jads crimp japs jae default 0 0 0 0 0 0 0 0 note: crimp controls all 16 lius. all other bits are for lius 1 ? 8 only. bit 7: receive impeda nce mode select (rimpms). when this bit is set, fully internal impedance match mode is selected, so rtip and rring require no external resistor. if this bit is set, the receiver line transformer must be a 1:1 turns ratio and the rtr bit set. when reset, ex ternal termination mode is selected and an external resistor is required to terminate the receive line. this external resistor will be adjusted internally to the correct termination value if partially internal impedance matching is turned on ( ts .rimpon = 1). bit 6: ais enable during loss (aisel). when this bit is set, an ais is sent to the system side upon detecting los for each channel. the individual liu register iaisel settings wil l be ignored when this bit is set. when reset, the iaisel register will have control. bit 5: short circuit protection disable (scpd). if this bit is set the short - circuit protection is disabled for all the transmitt ers. the individual liu register iscpd settings will be ignored when this bit is set. when reset, the iscpd register will have control. bit 4: code (code). if this bit is set ami encoder/decoder is selected. t he lcs register settings will be ignored when this bit is set . if reset, the lcs register will have control. bit 3: jitter attenuator depth select (jads). if this bit is set the jitter attenuator fifo depth is 128 bits. the settings in the ijafds register will be ignored if this register is set . if reset the ijafds register wil l have control. bit 2: calibrate receive internal termination (crimp). a low -to - high transition on this bit initiates a calibration cycle for the receive internal termination. this requires a 16k ? 1% resistor on the resref pin. bit 2 of the gc register at address 0x2f must also be set to enable calibration. while this bit is set, rsl4 .4 (0x0f in individual bank) will indicate the status of the calibration cycle. bit 1: jitter attenuator position select (japs). when the japs bit is set high, the jitter attenuator will be in the receive path and when default or set low in the transmit path. these settings can be changed for an individual liu by settings in the ijaps register. note tha t when bit jae is set, the settings in the ijaps register will be ignored. bit 0: jitter attenuator enable (jae). when this bit is set the jitter attenuator is enabled. the settings in the ijae register will be ignored if this register is set. if reset, the ijae register will have control.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 57 of 120 register address (lius 9 ? 16): 2fh bit # 7 6 5 4 3 2 1 0 name rimpms aisel scpd code jads calen japs jae default 0 0 0 0 0 0 0 0 bit 7: rece ive impedance mode select (rimpms). when this bit is set, the fully internal receive impedance matching mode is selected, so rtip and rring require no external resistor. if this bit is set, the receiver line transformer must be a 1:1 turns ratio and the rt r bit set. when reset and ts .rimpon = 1, partially internal receive impedance matching mode is selected and an external resistor is required to terminate the receive line. this external resistor will be adjusted internally to the correct termination value. bit 6: ais enable during loss (aisel). when this bit is set, an ais is sent to the system side upon detecting los for each channel. the individual liu register iaisel settings will be ignored when this bit is set. when reset, the iaisel register will have control. bit 5: short circuit protection disable (scpd). if this bit is set the short - circuit protection is disabled for all the transmitter s. the individual liu register iscpd settings will be ignored when this bit is set. when reset, the iscpd register will have control. bit 4: code (code). if this bit is set ami e ncoder/decoder is selected. t he lcs register settings will be ignored when this bit is set . if reset, the lcs register will have control. bit 3: jitter attenuator depth select (jads). if this bit is set the jitter attenuator fifo depth is 128 bits. the settings in the ijafds register will be ignored if this register is set . if reset the ijafds register will have control. bit 2: calibrate receive impedance match (calen). this bit must be set to enable calibration of the receive termination. if this bit is set and a 16k ? resistor is on the resref pin, then a low -to - high transition on the crimp bit will initiate a calibration cycle for the receive internal termination. the user should wait at least 5 s before setting the crimp bit. bit 1: jitter attenuator position select (japs). when the japs bit is set, the jitter attenuator will be in the receive path for each channel. the individual liu register ijaps settings will be ignored when this bit is set. when reset, the ijaps register will have control. bit 0: jitter attenuator enable (jae) . when this bit is set the jitter attenuator is enabled. the settings in the ijae register will be ignored if this register is set. if reset, the ijae register will have control.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 58 of 120 register name: tst register descripti on: template select transmitter register address (lius 1 ? 8): 10h bit # 7 6 5 4 3 2 1 0 name jabws1 jabws0 rhpmc ? ? tst2 tst1 tst0 default 0 0 0 0 0 0 0 0 bits 7 and 6: jitter attenuator bandwidth selection [1:0] (jabws[1:0]). in e1 mode, jabws[1:0] is used to control the bandwidth of the jitter attenuator according to the following table: jabws bandwidth (hz) 00 0.625 01 1.25 10 2.5 11 5 bit 5: receive hitless protection mode control (rhpmc). when this bit is set, the receive impedance match on/off selection will be controlled by the oe pin. if oe is high, receive impedance match is on. if oe is low, receive impedance match is off (internal impedance to rtip and rring is high impedance). when this bit is reset, the rimpon register bit will con trol receive impedance match. bits 2 to 0: tst template select transceiver [2:0] (tst[2:0]) . tst[2:0] is used to select the transceiver that the transmit template select register (0x11) will configure for lius 1 ? 8. see table 6 -11 . register address (lius 9 ? 16): 30h bit # 7 6 5 4 3 2 1 0 name jabws1 jabws0 rhpmc ? ? tst2 tst1 tst0 default 0 0 0 0 0 0 0 0 bits 7 and 6: jitter attenuator bandwidth selection [1:0] (jabws[1:0]). in e1 mode, jabws[1:0] is used to control the bandwidth of the jitter attenuator according to the following table: jabws bandwidth (hz) 00 0.625 01 1.25 10 2.5 11 5 bit 5: receive hitless protection mode control (rhpmc). when this bit is set, the receive impedance match on/ off selection will be controlled by the oe pin. if oe is high, receive impedance match is on. if oe is low, receive impedance match is off (internal impedance to rtip and rring is high impedance). when this bit is reset, the rimpon register bit will contro l receive impedance match. bits 2 to 0: tst template select transceiver [2:0] (tst[2:0]) . tst[2:0] is used to select the transceiver that the transmit template select register (0x11) will configure for lius 9 ? 16. see table 6 -12 .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 59 of 120 table 6 - 11 . tst template select transmitter register (lius 1 ? 8) tst[2:0] channel tst[2:0] channel 000 1 100 5 001 2 101 6 010 3 110 7 011 4 111 8 table 6 - 12 . tst template select transmitter register (lius 9 ? 16) tst[2:0] channel tst[2:0] channel 000 9 100 13 001 10 101 14 010 11 110 15 011 12 111 16
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 60 of 120 register name: ts register description: template select register address (lius 1 ? 8): 11h register address (lius 9 ? 16): 31h bit # 7 6 5 4 3 2 1 0 name rimpon timpoff ? ? timprm ts2 ts1 ts0 default 0 0 0 0 0 0 0 0 note: this register configures each liu individually. this register configures the liu selected by tst .tst[2:0]. bit 7: receive impedance match on (rimpon). if this bit is set, internal receive impedance matching is turned on. otherwise, the receiver is in high impedance. note that the oe pin can have control instead of this bit when th e tst .rhpmc bit is set. bit 6: transmit impedance termination off (timpoff). if this bit is set all the internal transmit terminating impedance is turned off. bit 3: transmit impedance receive match (timprm). this bit sel ects the internal transmit termination impedance and receive impedance match for e1 mode and t1/j1 mode. 0 = 75 ? for e1 mode or 100 ? for t1 mode. 1 = 120 ? for e1 mode or 110 ? for j1 mode. bits 2 to 0: template selection [2:0] (ts[2:0]). bits ts[2:0] ar e used to select e1 or t1/j1 mode, the template, and the settings for various cable lengths. the impedance termination for the transmitter and impedance match for the receiver are specified by bit timprm. see table 6 - 13 for bit selection of ts[2:0]. table 6 - 13 . template selection template selection ts[2:0] line length (ft) cable loss (db) impedance ( ? ) 011 0 ? 133 abam 0.6 100/110 100 133 ? 266 abam 1.2 100/110 101 266 ? 399 abam 1.8 100/110 110 399 ? 533 abam 2.4 100/110 111 533 ? 655 abam 3.0 100/110 000 g.703 coaxial and twisted pair cable 75/120 001 and 010 reserved ? ?
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 61 of 120 register name: oe register description: output enable configuration register address ( lius 1 ? 8): 12h bit # 7 6 5 4 3 2 1 0 name oe8 oe7 oe6 oe5 oe4 oe3 oe2 oe1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 32h bit # 7 6 5 4 3 2 1 0 name oe16 oe15 oe14 oe13 oe12 oe11 oe10 oe9 default 0 0 0 0 0 0 0 0 bits 7 to 0: output en able channel n (oe n ). when this bit is reset, the transmitter output for liu n is high impedance. when this bit is set, the transmitter output for liu n is enabled. note that the oe pin will override this setting when low. register name: ais register desc ription: alarm indication signal status register address (lius 1 ? 8): 13h bit # 7 6 5 4 3 2 1 0 name ais8 ais7 ais6 ais5 ais4 ais3 ais2 ais1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 33h bit # 7 6 5 4 3 2 1 0 name ais16 ais15 ais14 ais 13 ais12 ais11 ais10 ais9 default 0 0 0 0 0 0 0 0 bits 7 to 0: alarm indication signal channel n (ais n ). this bit will be set when ais is detected for liu n . the criteria for ais selection is detailed in section 5.5.7 . the selection of the ais criteria is done by settings in the lascs (0d) register.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 62 of 120 register name: aisie register description: ais interrupt enable register address (lius 1 ? 8): 14h bit # 7 6 5 4 3 2 1 0 name aisie8 aisie7 aisie6 aisie5 aisie4 aisie3 aisie2 aisie1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 34h bit # 7 6 5 4 3 2 1 0 name aisie16 aisie15 aisie14 aisie13 aisie12 aisie11 aisie10 aisie9 default 0 0 0 0 0 0 0 0 bits 7 to 0: a is interrupt mask channel n (aisie n ). when this bit is set, interrupts can be generated for liu n if ais status transitions. register name: aisis register description: ais interrupt status register address (lius 1 ? 8): 15h bit # 7 6 5 4 3 2 1 0 name aisis8 aisis7 aisis6 aisis5 aisis4 aisis3 aisis2 aisis1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 35h bit # 7 6 5 4 3 2 1 0 name aisis16 aisis15 aisis14 aisis13 aisis12 aisis11 aisis10 aisis9 default 0 0 0 0 0 0 0 0 bits 7 to 0: ais in terrupt status channel n (aisis n ). this bit is set when ais ransitions from a ?0 to 1? or ?1 to 0? and interrupts are enabled by the aisie (14) register for liu n . if set, this bit is cleared on a read operation or when the interrupt enable register is disabled.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 63 of 120 register name: addp register description: address pointer for bank selection register address (lius 1 ? 8): 1fh register address (lius 9 ? 16): 3fh bit # 7 6 5 4 3 2 1 0 name addp7 addp6 addp5 addp4 addp3 add p2 addp1 addp0 default 0 0 0 0 0 0 0 0 bits 7 to 0: address pointer (addp). this pointer is used to switch between pointing to the primary registers, the secondary registers, individual registers, and bert registers. see table 6 -14 for bank selection. the register space contains control for channels 1 to 8 from address 00 hex to 1f hex and a duplicate set of registers for control of channels 9 to 16 from address 20 hex to 3f hex. the addp at address 1f h ex select the banks for the set of registers for lius 1 ? 8. the addp register at address 3f select the banks for the set of registers for lius 9 ? 16. table 6 - 14 . address pointer bank selection addp[7:0] (hex) ba nk name 00 primary bank aa secondary bank 01 individual liu bank 02 bert bank 6.1.2 secondary register bank the addp register must be set to aah in order to access this bank. register name: srms register description: single - rail mode select register ad dress (lius 1 ? 8): 00h bit # 7 6 5 4 3 2 1 0 name srms8 srms7 srms6 srms5 srms4 srms3 srms2 srms1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 20h bit # 7 6 5 4 3 2 1 0 name srms16 srms15 srms14 srms13 srms12 srms11 srms10 srms9 default 0 0 0 0 0 0 0 0 bits 7 to 0: single - rail mode select channel n (srms n ). when this bit is set single - rail mode is selected for the system transmit and receive n . if this bit is reset, dual - rail is selected.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 64 of 120 register name: lcs register description: line code selection register address (lius 1 ? 8): 01h bit # 7 6 5 4 3 2 1 0 name lcs8 lcs7 lcs6 lcs5 lcs4 lcs3 lcs2 lcs1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 21h bit # 7 6 5 4 3 2 1 0 name lcs16 lcs15 lcs14 lcs13 lcs12 lcs11 lcs10 lcs 9 default 0 0 0 0 0 0 0 0 bits 7 to 0: line code select channel n (lcs n ). when this bit is set ami encoding/decoding is selected for liu n . if reset, b8zs or hdb3 encoding/decoding is selected for liu n . note that if the gc .code register bit is set it will ignore this register. register name: rpde register description: receive power - down enable register address (lius 1 ? 8): 03h bit # 7 6 5 4 3 2 1 0 name rpde8 rpde7 rpde6 rpde5 rpde4 rpde3 rpde2 rpde1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 23h bit # 7 6 5 4 3 2 1 0 name rpde16 rpde15 rpde14 rpde13 rpde12 rpde11 rpde10 rpde9 default 0 0 0 0 0 0 0 0 bits 7 to 0: receive power - down enable channel n (rpde n ). when this bit is set the receiver for liu n is powered down. register name: tpde register description: transmit power - down enable register address (lius 1 ? 8): 04h bit # 7 6 5 4 3 2 1 0 name tpde8 tpde7 tpde6 tpde5 tpde4 tpde3 tpde2 tpde1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 1 6): 24h bit # 7 6 5 4 3 2 1 0 name tpde16 tpde15 tpde14 tpde13 tpde12 tpde11 tpde10 tpde9 default 0 0 0 0 0 0 0 0 bits 7 to 0: transmit power - down enable channel n (tpde n ). when this bit is set the transmitter for liu n is powered down.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 65 of 120 register na me: ezde register description: excessive zero detect enable register address (lius 1 ? 8): 05h bit # 7 6 5 4 3 2 1 0 name ezde8 ezde7 ezde6 ezde5 ezde4 ezde3 ezde2 ezde1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 25h bit # 7 6 5 4 3 2 1 0 name ezde16 ezde15 ezde14 ezde13 ezde12 ezde11 ezde10 ezde9 default 0 0 0 0 0 0 0 0 bits 7 to 0: excessive zero detect enable channel n (ezde n ). when this bit is reset excessive zero detection is disabled for liu n . when this bit is set excessive zero detect enable is enabled. excessive zero detection is only relevant when hdb3 or b8zs decoding is enabled ( lcs register). register name: cvdeb register description: code violation detect enable bar register address ( lius 1 ? 8): 06h bit # 7 6 5 4 3 2 1 0 name cvdeb8 cvdeb7 cvdeb6 cvdeb5 cvdeb4 cvdeb3 cvdeb2 cvdeb1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 26h bit # 7 6 5 4 3 2 1 0 name cvdeb16 cvdeb15 cvdeb14 cvdeb13 cvdeb12 cvdeb11 cvdeb10 cvdeb9 default 0 0 0 0 0 0 0 0 bits 7 to 0: code violation detect enable bar channel n (cvdeb n ). if this bit is set, code violation detection is disabled for the liu n . if this bit is reset, code violation detection is enabled. code violation detection is only r elevant when hdb3 decoding is enabled ( lcs register).
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 66 of 120 6.1.3 individual liu register bank the addp register must be set to 01h to access this bank. register name: ijae register description: individual jitter attenuator enable register address (lius 1 ? 8): 00h bit # 7 6 5 4 3 2 1 0 name ijae8 ijae7 ijae6 ijae5 ijae4 ijae3 ijae2 ijae1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 20h bit # 7 6 5 4 3 2 1 0 name ijae16 ijae15 ijae14 ijae13 ijae12 ijae11 ijae10 ija e9 default 0 0 0 0 0 0 0 0 bits 7 to 0: individual jitter attenuator enable channel n (ijae n ). when this bit is set, the liu jitter attenuator n is enabled. note that if the gc .jae register bit is set, this register will be ignored. register name: ijaps register description: individual jitter attenuator position select register address (lius 1 ? 8): 01h bit # 7 6 5 4 3 2 1 0 name ijaps8 ijaps7 ijaps6 ijaps5 ijaps4 ijaps3 ijaps2 ijaps1 default 0 0 0 0 0 0 0 0 regis ter address (lius 9 ? 16): 21h bit # 7 6 5 4 3 2 1 0 name ijaps16 ijaps15 ijaps14 ijaps13 ijaps12 ijaps11 ijaps10 ijaps9 default 0 0 0 0 0 0 0 0 bits 7 to 0: individual jitter attenuator position select channel n (ijaps n ). when this bit is set high, th e jitter attenuator is in the receive path n ; when this bit is default or set low the jitter attenuator is in the transmit path n . note that if the gc .jae register bit is set, this register will be ignored.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 67 of 120 register name: ijafds register description: individual jitter attenuator fifo depth select register address (lius 1 ? 8): 02h bit # 7 6 5 4 3 2 1 0 name ijafds8 ijafds7 ijafds6 ijafds5 ijafds4 ijafds3 ijafds2 ijafds1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 22h bit # 7 6 5 4 3 2 1 0 name ijafds16 ijafds15 ijafds14 ijafds13 ijafds12 ijafds11 ijafds10 ijafds9 default 0 0 0 0 0 0 0 0 bits 7 to 0: individual jitter attenuator fifo depth select n (ijafds n ). when this bit is set for liu n the jitter att enuator fifo depth will be 128 bits. when reset the jitter attenuator fifo depth will be 32 bits. note that if the gc .ijafds register bit is set, this register will be ignored. register name: ijaflt register description: individual jitter attenuator fifo limit trip register address (lius 1 ? 8): 03h bit # 7 6 5 4 3 2 1 0 name ijaflt8 ijaflt7 ijaflt6 ijaflt5 ijaflt4 ijaflt3 ijaflt2 ijaflt1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 23h bit # 7 6 5 4 3 2 1 0 name ijaflt16 ijaflt15 ijaflt14 ijaflt13 ijaflt12 ijaflt11 ijaflt10 ijaflt9 default 0 0 0 0 0 0 0 0 bits 7 to 0: individual jitter attenuator fifo limit trip n (ijaflt n ). set when the jitter attenuator fifo reaches to within 4 bits of its useful lim it for transmitter n . this bit will be cleared when read. register name: iscpd register description: individual short - circuit protection disable register address (lius 1 ? 8): 04h bit # 7 6 5 4 3 2 1 0 name iscpd8 iscpd7 iscpd6 iscpd5 iscpd4 iscpd3 is cpd2 iscpd1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 24h bit # 7 6 5 4 3 2 1 0 name iscpd16 iscpd15 iscpd14 iscpd13 iscpd12 iscpd11 iscpd10 iscpd9 default 0 0 0 0 0 0 0 0 bits 7 to 0: individual short - circuit protection disable n . (is cpd n ). when this bit is set the short - circuit protection is disabled for the individual transmitter n . note that if the gc . scpd register bit is set, the settings in this register will be ignored.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 68 of 120 register name: iaisel reg ister description: individual ais select register address (lius 1 ? 8): 05h bit # 7 6 5 4 3 2 1 0 name iaisel8 iaisel7 iaisel6 iaisel5 iaisel4 iaisel3 iaisel2 iaisel1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 25h bit # 7 6 5 4 3 2 1 0 n ame iaisel16 iaisel15 iaisel14 iaisel13 iaisel12 iaisel11 iaisel10 iaisel9 default 0 0 0 0 0 0 0 0 bits 7 to 0: individual ais enable during loss n (iaisel n ). when this bit is set, individual ais enable during loss is enabled for the individual receiver n , and ais is sent to the system side upon detection of an los. note that if the gc .aisel register bit is set, the settings in this register will be ignored.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 69 of 120 register name: mc register description: master clock select register address: 06h bit # 7 6 5 4 3 2 1 0 name pclki1 pclki0 teclke clkae mps1 mps0 freqs plle default 0 0 0 0 0 0 0 0 bits 7 and 6: pll clock input [1:0] (pclki[1:0]). these bits select the input into to the pll. 00: mclk is used. 01: rclk1 to 8 is used based on the selection in register ccr . 10: rclk9 to 16 is used based on the selection in register ccr. 11: reserved. bit 5: t1/e1 clock enable (teclke). when this bit is set the teclk output is enabled. if not set teclk will be disabled and the teclk output is a los output. teclk requires plle to be set for correct functionality. bit 4: clock a enable (clkae). when this bit is set the clka output is enabled. if not set clka will be disabled and the clka out put is a los output. clka requires plle to be set for correct functionality. bits 3 and 2: master period select [1:0] (mps[1:0]). these bits mps[1:0] selects the external mclk frequency for the ds26324. see table 6 -15 for details. this register when written to will also controller functionality of channels 9 to 16. bit 1: frequency select (freqs). in conjunction with mps[1:0] selects the external mclk frequency for the ds26324. if this bit is set the exte rnal master clock can be 1.544mhz or multiple thereof. if not set the external master clock can be 2.048mhz or multiple thereof. see table 6 -15 for details. this register when written to will also controll er functionality of channels 9 to 16. bit 0: phase lock loop enable (plle). when this bit is set the phase lock loop is enabled. if not set mclk will be the applied input clock. table 6 - 15 . ds26324 mclk sele ctions plle mps1, mps0 mclk, mhz 50ppm freqs mode 0 xx 1.544 x t1 0 xx 2.048 x e1 1 00 1.544 1 t1/j1 or e1 1 01 3.088 1 t1/j1 or e1 1 10 6.176 1 t1/j1 or e1 1 11 12.352 1 t1/j1 or e1 1 00 2.048 0 t1/j1 or e1 1 01 4.096 0 t1/j1 or e1 1 10 8.192 0 t1/j1 or e1 1 11 16.384 0 t1/j1 or e1
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 70 of 120 register name: rsmm1 register description: receive sensitivity monitor mode 1 register address (lius 1 ? 8): 08h bit # 7 6 5 4 3 2 1 0 name rtr2 c2rsm2 c2rsm1 c2rsm0 rtr1 c1rsm2 c1rsm1 c1rsm0 default 0 0 0 0 0 0 0 0 bit 7: receiver transformer turns ratio channel 2 (rtr2). if this bit is set the turns ratio is 1:1 on the receiver side. this bit should be set when a 1:1 receiver transformer is used. note that in order to use fully internal receive impedance term ination, a 1:1 transformer must be used and this bit must be set to 1. bits 6 to 4: channel 2 receive sensitivity/monitor select [2:0] (c2rsm[2:0]). bits c2rsm[2:0] are used to select the receiver sensitivity level and the monitor mode resistive gain. see table 6 -16 . bit 3: receiver transformer turns ratio channel 1 (rtr1). if this bit is set the turns ratio is 1:1 on the receiver side. this bit should be set when a 1:1 receiver transformer is used. note th at in order to use the fully internal receive impedance termination, a 1:1 transformer must be used and this bit must be set to 1. bits 2 to 0: channel 1 receive sensitivity/monitor select [2:0] (c1rsm[2:0]). bits c1rsm[2:0] are used to select the receiver sensitivity level and the monitor mode resistive gain. see table 6 -16 . register address (lius 9 ? 16): 28h bit # 7 6 5 4 3 2 1 0 name rtr10 c10rsm2 c10rsm1 c10rsm0 rtr9 c9rsm2 c9rsm1 c9rsm0 default 0 0 0 0 0 0 0 0 bit 7: receiver transformer turns ratio channel 10 (rtr10). if this bit is set the turns ratio is 1:1 on the receiver side. this bit should be set when a 1:1 receiver transformer is used. note that in order to use fully internal receive impe dance termination, a 1:1 transformer must be used and this bit must be set to 1. bits 6 to 4: channel 10 receive sensitivity/monitor select [2:0] (c10rsm[2:0]). bits c10rsm[2:0] are used to select the receiver sensitivity level and the monitor mode resisti ve gain. see table 6 -16 . bit 3: receiver transformer turns ratio channel 9 (rtr9). if this bit is set the turns ratio is 1:1 on the receiver side. this bit should be set when a 1:1 receiver transformer is used. note that in order to use the fully internal receive impedance termination, a 1:1 transformer must be used and this bit must be set to 1. bits 2 to 0: channel 9 receive sensitivity/monitor select [2:0] (c9rsm[2:0]). bits c9rsm[2:0] are used to select the receiver sensitivity level and the monitor mode resistive gain. see table 6 -16 .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 71 of 120 register name: rsmm2 register description: receive sensitivity monitor mode 2 register address (lius 1 ? 8): 09h bit # 7 6 5 4 3 2 1 0 name rtr4 c4rsm2 c4rsm1 c4rsm0 rtr3 c3rsm2 c3rsm1 c3rsm0 default 0 0 0 0 0 0 0 0 bit 7: receiver transformer turns ratio channel 4 (rtr4). if this bit is set the turns ratio is 1:1 on the receiver side. this bit should be set when a 1 :1 receiver transformer is used. note that in order to use fully internal receive impedance termination, a 1:1 transformer must be used and this bit must be set to 1. bit 6 to 4: channel 4 receive sensitivity/monitor select [2:0] (c4rsm[2:0]). bits c4rsm[2 :0] are used to select the receiver sensitivity level and the monitor mode resistive gain. see table 6 -16 . bit 3: receiver transformer turns ratio channel 3 (rtr3). if this bit is set the turns ratio is 1: 1 on the receiver side. this bit should be set when a 1:1 receiver transformer is used. note that in order to use the fully internal receive impedance termination, a 1:1 transformer must be used and this bit must be set to 1. bit 2 to 0: channel 3 receive sensitivity/monitor select [2:0] (c3rsm[2:0]). bits c3rsm[2:0] are used to select the receiver sensitivity level and the monitor mode resistive gain. see table 6 -16 . register address (lius 9 ? 16): 29h bi t # 7 6 5 4 3 2 1 0 name rtr12 c12rsm2 c12rsm1 c12rsm0 rtr11 c11rsm2 c11rsm1 c11rsm0 default 0 0 0 0 0 0 0 0 bit 7: receiver transformer turns ratio channel 12 (rtr12). if this bit is set the turns ratio is 1:1 on the receiver side. this bit should be set when a 1:1 receiver transformer is used. note that in order to use fully internal receive impedance termination, a 1:1 transformer must be used and this bit must be set to 1. bits 6 to 4: channel 12 receive sensitivity/monitor select [2:0] (c12rsm[2:0] ). bits c12rsm[2:0] are used to select the receiver sensitivity level and the monitor mode resistive gain. see table 6 -16 . bit 3: receiver transformer turns ratio channel 11 (rtr11) . if this bit is set the rurns ratio is 1:1 on the receiver side. this bit should be set when a 1:1 receiver transformer is used. note that in order to use the fully internal receive impedance termination, a 1:1 transformer must be used and this bit must be set to 1. bits 2 to 0: channel 11 receive sensitivity/monitor select [2:0] (c11rsm[2:0]). bits c11rsm[2:0] are used to select the receiver sensitivity level and the monitor mode resistive gain. see table 6 -16 .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 72 of 120 register name: rsmm3 register description: receive sensitivity monitor mode 3 register address (lius 1 ? 8): 0ah bit # 7 6 5 4 3 2 1 0 name rtr6 c6rsm2 c6rsm1 c6rsm0 rtr5 c5rsm2 c5rsm1 c5rsm0 default 0 0 0 0 0 0 0 0 bit 7: receiver transformer turns ratio channel 6 (rtr6). if this bit is set the turns ratio is 1:1 on the receiver side. this bit should be set when a 1:1 receiver transformer is used. note that in order to use fully internal receive impedance termination, a 1:1 transformer must be used and this bit mus t be set to 1. bits 6 to 4: channel 6 receive sensitivity/monitor select [2:0] (c6rsm[2:0]). bits c6rsm[2:0] are used to select the receiver sensitivity level and the monitor mode resistive gain. see table 6 -16 . bit 3: receiver transformer turns ratio channel 5 (rtr5). if this bit is set the turns ratio is 1:1 on the receiver side. this bit should be set when a 1:1 receiver transformer is used. note that in order to use the fully internal receive impedance termination, a 1:1 transformer must be used and this bit must be set to 1. bits 2 to 0: channel 5 receive sensitivity/monitor select [2:0] (c5rsm[2:0]). bits c5rsm[2:0] are used to select the receiver sensitivity level and the monitor mode resistive gain. see table 6 -16 . register address (lius 9 ? 16): 2ah bit # 7 6 5 4 3 2 1 0 name rtr14 c14rsm2 c14rsm1 c14rsm0 rtr13 c13rsm2 c13rsm1 c13rsm0 default 0 0 0 0 0 0 0 0 bit 7: receiver transformer turns rat io channel 14 (rtr14). if this bit is set the turns ratio is 1:1 on the receiver side. this bit should be set when a 1:1 receiver transformer is used. note that in order to use fully internal receive impedance termination, a 1:1 transformer must be used an d this bit must be set to 1. bits 6 to 4: channel 14 receive sensitivity/monitor select [2:0] (c14rsm[2:0]). bits c14rsm[2:0] are used to select the receiver sensitivity level and the monitor mode resistive gain. see table 6 -16 . bit 3: receiver transformer turns ratio channel 13 (rtr13) . if this bit is set the turns ratio is 1:1 on the receiver side. this bit should be set when a 1:1 receiver transformer is used. note that in order to use the fully internal receive impedance termination, a 1:1 transformer must be used and this bit must be set to 1. bits 2 to 0: channel 13 receive sensitivity/monitor select [2:0] (c13rsm[2:0]). bits c13rsm[2:0] are used to select the receiver sensitivity level and the monitor mode resistive gain. see table 6 -16 .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 73 of 120 register name: rsmm4 register description: receive sensitivity monitor mode 4 register address (lius 1 ? 8): 0bh bit # 7 6 5 4 3 2 1 0 name rtr8 c8rsm2 c8rsm1 c8r sm0 rtr7 c7rsm2 c7rsm1 c7rsm0 default 0 0 0 0 0 0 0 0 bit 7: receiver transformer turns ratio channel 8 (rtr8). if this bit is set the turns ratio is 1:1 on the receiver side. this bit should be set when a 1:1 receiver transformer is used. note that in order to use fully internal receive impedance termination, a 1:1 transformer must be used and this bit must be set to 1. bits 6 to 4: channel 8 receive sensitivity/monitor select [2:0] (c8rsm[2:0]). bits c8rsm[2:0] are used to select the receiver sensitivi ty level and the monitor mode resistive gain. see table 6 -16 . bit 3: receiver transformer turns ratio channel 7 (rtr7). if this bit is set the turns ratio is 1:1 on the receiver side. this bit should be se t when a 1:1 receiver transformer is used. note that in order to use the fully internal receive impedance termination, a 1:1 transformer must be used and this bit must be set to 1. bits 2 to 0: channel 7 receive sensitivity/monitor select [2:0] (c7rsm[2:0] ). bits c7rsm[2:0] are used to select the receiver sensitivity level and the monitor mode resistive gain. see table 6 -16 . register address (lius 9 ? 16): 2bh bit # 7 6 5 4 3 2 1 0 name rtr16 c16rsm2 c16r sm1 c16rsm0 rtr15 c15rsm2 c15rsm1 c15rsm0 default 0 0 0 0 0 0 0 0 bit 7: receiver transformer turns ratio channel 16 (rtr16). if this bit is set the turns ratio is 1:1 on the receiver side. this bit should be set when a 1:1 receiver transformer is used. note that in order to use fully internal receive impedance termination, a 1:1 transformer must be used and this bit must be set to 1. bit 6 to 4: channel 16 receive sensitivity/monitor select [2:0] (c16rsm[2:0]). bits c16rsm[2:0] are used to select the re ceiver sensitivity level and the monitor mode resistive gain. see table 6 -16 . bit 3: receiver transformer turns ratio channel 15 (rtr15). if this bit is set the turns ratio is 1:1 on the receiver side. thi s bit should be set when a 1:1 receiver transformer is used. note that in order to use the fully internal receive impedance termination, a 1:1 transformer must be used and this bit must be set to 1. bits 2 to 0: channel 15 receive sensitivity/monitor selec t [2:0] (c15rsm[2:0]). bits c15rsm[2:0] are used to select the receiver sensitivity level and the monitor mode resistive gain. see table 6 -16 . table 6 - 16 . rec eiver sensitivity/monitor mode gain selection receiver monitor mode disabled c n rsm[2:0], t1/ e1 mode receiver sensitivity (maximum loss) (db) receiver monitor mode gain settings (db) loss declaration level (db) no flat gain 000 12 0 15 no flat gain 001 1 8 0 21 receiver monitor mode enabled c n rsm[2:0] max cable loss receiver monitor mode gain settings ? flat gain 100 30 14 37 flat gain 101 22.5 20 45.5
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 74 of 120 register name: rsl1 register description: receive signal level indicator 1 register address (lius 1 ? 8): 0ch bit # 7 6 5 4 3 2 1 0 name c2rsl3 c2rsl2 c2rsl1 c2rsl0 c1rsl3 c1rsl2 c1rsl1 c1rsl0 default 0 0 0 0 0 0 0 0 bits 7 to 4: channel 2 receive signal level [3:0] (c2rsl[3:0]). c2rsl[3:0] bits provide the receive signal llevel as shown in table 6 -17 . bits 3 to 0: channel 1 receive signal level [3:0] (c1rsl[3:0]). c1rsl[3:0] bits provide the receive signal level as shown in table 6 -17 . register address (lius 9 ? 16): 2ch bit # 7 6 5 4 3 2 1 0 name c10rsl3 c10rsl2 c10rsl1 c10rsl0 c9rsl3 c9rsl2 c9rsl1 c9rsl0 default 0 0 0 0 0 0 0 0 bits 7 to 4: channel 10 receive signal level [3:0] (c10rsl[3:0]). c10rsl[3:0] bits provide the receive signal lev el as shown in table 6 -17 . bits 3 to 0: channel 9 receive signal level [3:0] (c9rsl[3:0]). c9rsl[3:0] bits provide the receive signal level as shown in table 6 -17 .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 75 of 120 table 6 - 17 . receiver signal level c n rsl3 to c n rsl0 receive level (db) t1 e1 0000 > - 2.5 > - 2.5 0001 - 2.5 to - 5 - 2.5 to - 5 0010 - 5 to - 7.5 - 5 to - 7.5 0011 - 7.5 to - 10 - 7.5 to - 10 0100 - 10 to - 12.5 - 10 to - 12.5 0101 - 12.5 to - 15 - 12.5 to - 15 0110 - 15 to - 17.5 - 15 to - 17.5 0111 - 17.5 to - 20 - 17.5 to ? 20 register name: rsl2 register description: receive signal level indicator 2 register address (lius 1 ? 8): 0dh bit # 7 6 5 4 3 2 1 0 name c4rsl3 c4rsl2 c4rsl1 c4rsl0 c3rsl3 c3rsl2 c3rsl1 c3rsl0 default 0 0 0 0 0 0 0 0 bits 7 to 4: channel 4 receive signal level [3:0] (c4rsl[3:0]). c4rsl[3:0] bits provide the receive signal level as shown in table 6 -17 . bits 3 to 0: channel 3 receive signal level [3:0] (c3rsl[3:0]). c3rsl[3:0] bits provide the receive signal level as shown in table 6 -17 . register address (lius 9 ? 16): 2dh bit # 7 6 5 4 3 2 1 0 name c12rsl3 c12rsl2 c12rsl1 c12rsl0 c11rsl3 c11rsl2 c11rsl1 c11rsl0 default 0 0 0 0 0 0 0 0 bits 7 to 4: channel 12 receive signal level [3:0] (c12rsl[3:0]). c12rsl[3:0] bits provide the receive signal level as shown in table 6 -17 . bits 3 to 0: channel 11 receive signal level [3:0] (c11rsl[3:0]). c11rsl[3:0] bits provide the receive signal level as shown in table 6 -17 .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 76 of 120 register name: rsl3 register description: receive signal level indicator 3 register address (lius 1 ? 8): 0eh bit # 7 6 5 4 3 2 1 0 name c6rsl3 c6rsl2 c6rsl1 c6rsl0 c5rsl3 c5rsl2 c5rsl1 c5rsl0 default 0 0 0 0 0 0 0 0 bits 7 to 4: channel 6 receive signal level [3:0] (c6 rsl[3:0]). c6rsl[3:0] bits provide the receive signal level as shown in table 6 -17 . bits 3 to 0: channel 5 receive signal level [3:0] (c5rsl[3:0]). c5rsl[3:0] bits provide the receive signal level as show n in table 6 -17 . register address (lius 9 ? 16): 2eh bit # 7 6 5 4 3 2 1 0 name c14rsl3 c14rsl2 c14rsl1 c14rsl0 c13rsl3 c13rsl2 c13rsl1 c13rsl0 default 0 0 0 0 0 0 0 0 bits 7 to 4: channel 14 receive signal level [3:0] (c14rsl[3:0]). c14rsl[3:0] bits provide the receive signal level as shown in table 6 -17 . bits 3 to 0: channel 13 receive signal level [3:0] (c13rsl[3:0]). c13rsl[3:0] bits provide the receive signal level as shown in table 6 -17 .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 77 of 120 register name: rsl4 register description: receive signal level indicator 4 register address (lius 1 ? 8): 0fh bit # 7 6 5 4 3 2 1 0 name c8rsl3 c8rsl2 c8r sl1 c8rsl0/ calstat c7rsl3 c7rsl2 c7rsl1 c7rsl0 default 0 0 0 0 0 0 0 0 bits 7 to 4: channel 8 receive signal level [3:0] (c8rsl[3:0]). c8rsl[3:0] bits provide the receive signal level as shown in table 6 -17 . bit 4: channel 8 receive signal level 0/calibration status (c8rsl0/calstat). when crimp is high, c8rsl0 will be replaced by a real - time status bit for the receive internal termination calibration circuit. if the bit is low, this indicates that the c alibration has not completed. if the bit is high, this indicates the calibration completed successfully. normally this bit should go high within 7 s of the low -to - high transition of the crimp bit. receive termination values will be updated subsequently. bi ts 3 to 0: channel 7 receive signal level [3:0] (c7rsl[3:0]). c7rsl[3:0] bits provide the receive signal level as shown in table 6 -17 . register address (lius 9 ? 16): 2fh bit # 7 6 5 4 3 2 1 0 name c16 rsl3 c16rsl2 c16rsl1 c16rsl0 c15rsl3 c15rsl2 c15rsl1 c15rsl0 default 0 0 0 0 0 0 0 0 bits 7 to 4: channel 16 receive signal level [3:0] (c16rsl[3:0]). c16rsl[3:0] bits provide the receive signal level as shown in table 6 -17 . bits 3 to 0: channel 15 receive signal level [3:0] (c15rsl[3:0]). c15rsl[3:0] bits provide the receive signal level as shown in table 6 -17 .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 78 of 120 register name: btcr register descrip tion: bit error rate tester control register address (lius 1 ? 8): 10h bit # 7 6 5 4 3 2 1 0 name bts2 bts1 bts0 ? ? ? ? berte default 0 0 0 0 0 0 0 0 note: this register enables the liu1 - liu8 bert. the bert can only connect to one liu at a time. the liu1 - liu8 bert operates independently of the liu9 - liu16 bert. bits 7 to 5: bit error rate transceiver select [2:0] (bts[2:0]). these bits bts[2:0] select the liu that the bert applies to (see table 6 -18 ) . this is only applicable if the berte bit is set. bit 0: bit error rate tester enable (berte). when this bit is set and 2 s have past, the bert will be enabled. the bert register set should be written and read to only after being enabled. the bert is only active for one liu at a time selected by bts[2:0]. this bit also forces the part into single - rail mode with hdb3/b8zs encoding enabled. register address (lius 9 ? 16): 30h bit # 7 6 5 4 3 2 1 0 name bts2 bts1 bts0 ? ? ? ? berte default 0 0 0 0 0 0 0 0 note: this register enables the liu9 - liu16 bert. the bert can only connect to one liu at a time. the liu9 - liu16 bert operates independently of the liu1 ? liu8 bert. bits 7 to 5: bit error rate transceiver select [2:0] (bts[2:0]) these bits bts[2:0] select the liu that the bert applies too (see table 6 -19 ). this is only applicable if the berte bit is set. bit 0: bit error rate tester enable (berte). when this bit is set and 2 s have past, the bert will be e nabled. the bert register set should be written and read to only after being enabled. the bert is only active for one liu at a time selected by bts[2:0]. this bit also forces the part into single - rail mode with hdb3/b8zs encoding enabled.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 79 of 120 table 6 - 18 . bit error rate transceiver select for channels 1 ? 8 register address bts2 bts1 bts0 channel bert applies to 10h 0 0 0 channel 1 10h 0 0 0 channel 2 10h 0 1 0 channel 3 10h 0 1 1 channel 4 10h 1 0 0 channel 5 1 0h 1 0 1 channel 6 10h 1 1 0 channel 7 10h 1 1 1 channel 8 table 6 - 19 . bit error rate transceiver select for channels 9 ? 16 register address bts2 bts1 bts0 channel bert applies to 30h 0 0 0 channel 9 30h 0 0 0 channel 10 30h 0 1 0 channel 11 30h 0 1 1 channel 12 30h 1 0 0 channel 13 30h 1 0 1 channel 14 30h 1 1 0 channel 15 30h 1 1 1 channel 16 register name: beir register description: bpv error insertion register address (lius 1 ? 8): 11h bit # 7 6 5 4 3 2 1 0 name beir8 beir7 beir6 beir5 beir4 beir3 beir2 beir1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 31h bit # 7 6 5 4 3 2 1 0 name beir16 beir15 beir14 beir13 beir12 beir11 beir10 beir9 default 0 0 0 0 0 0 0 0 bits 7 to 0 : bpv error insertion register n (beir n ). a 0 - to - 1 transition on this bit will cause a single bipolar violation (bpv) to be inserted into the transmit data stream channel n . this bit must be cleared and set again for a subsequent error to be inserted. this is only applicable in single - rail mode.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 80 of 120 register name: lvds register description: line violation detect status register address (lius 1 ? 8): 12h bit # 7 6 5 4 3 2 1 0 name lvds8 lvds7 lvds6 lvds5 lvds4 lvds3 lvds2 lvds1 default 0 0 0 0 0 0 0 0 re gister address (lius 9 ? 16): 32h bit # 7 6 5 4 3 2 1 0 name lvds16 lvds15 lvds14 lvds13 lvds12 lvds11 lvds10 lvds9 default 0 0 0 0 0 0 0 0 bits 7 to 0: line violation detect status n (lvds n ). a bipolar violation, a code violation, or excessive zeros w ill cause the associated lvds n bit to latch. this bit will be cleared on a read operation. the lvds register captures the first violation within a three clock period window. if a second violation occurs after the first violation within the three clock peri od window, then the second violation will not be latched even if a read to the lvds register was performed. excessive zeros need to be enabled by the ezde register for detection by this register. code violations are onl y relevant when in hdb3 mode and can be disabled for detection by this register by setting the cvdeb register. register name: rclki register description: receive clock invert register address (lius 1 ? 8): 13h bi t # 7 6 5 4 3 2 1 0 name rclki8 rclki7 rclki6 rclki5 rclki4 rclki3 rclki2 rclki1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 33h bit # 7 6 5 4 3 2 1 0 name rclki16 rclki15 rclki14 rclki13 rclki12 rclki11 rclki10 rclki9 default 0 0 0 0 0 0 0 0 bit 7 to 0: receive clock invert n (rclki n ). when this bit is set the rclk for channel n is inverted. this aligns rpos/rneg on the falling edge of rclk. when reset or default rpos/rneg is aligned on the rising edge of rclk.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 81 of 120 register name: tclki r egister description: transmit clock invert register address (lius 1 ? 8): 14h bit # 7 6 5 4 3 2 1 0 name tclki8 tclki7 tclki6 tclki5 tclki4 tclki3 tclki2 tclki1 default 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 34h bit # 7 6 5 4 3 2 1 0 name tc lki16 tclki15 tclki14 tclki13 tclki12 tclki11 tclki10 tclki9 default 0 0 0 0 0 0 0 0 bits 7 to 0: transmit clock invert n (tclki n ). when this bit is set the expected tclk for channel n is inverted. tpos/tneg should be aligned on the falling edge of tclk . when reset or default tpos/tneg should be aligned on the rising edge of tclk.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 82 of 120 register name: ccr register description: clock control register address: 15h bit # 7 6 5 4 3 2 1 0 name pclks2 pclks1 pclks0 teclks clka3 clka2 clka1 clka0 default 0 0 0 0 0 0 0 0 bits 7 to 5: pll clock select (pclks[2:0]). these bits determine the rclk that is to be used as the input to the pll. if an los is detect for the channel that rclk is recovered from, the pll will switch to mclk until the los is cleared. when the los is cleared rclk will be used again. see table 6 -20 for rclk selection. mc .pclki[1:0] must be set to ?01? or ?10? in order for these settings to take effect. table 6 - 20 . pll clock select pclks[2:0] pll clock selected mc . pclki[1:0]=01 pll clock selected mc . pclki[1:0]=10 000 rclk1 rclk9 001 rclk2 rclk10 0 10 rclk3 rclk11 011 rclk4 rclk12 100 rclk5 rclk13 101 rclk6 rclk14 110 rclk7 rclk15 111 rclk8 rclk16 bit 4: t1/e1 clock select (teclks). when this bit is set the t1/e1 clock output is 2.048mhz. when this bit is reset the t1/e1 clock rate is 1.544mhz bits 3 to 0: clock a select (clka[3:0]). these bits select the output frequency for clka pin. see table 6 -21 for available frequencies. for best jitter performance, select mclk as the source for clka and input a 2.048mhz mclk. table 6 - 21 . clock a select clka[3:0] clka (hz) 0000 2.048m 0001 4.096m 0010 8.192m 0011 16.384m 0100 1.544m 0101 3.088m 0110 6.176m 0111 12.352m 1000 1.536m 1001 3.072m 1010 6 .144m 1011 12.288m 1100 32k 1101 64k 1110 128k 1111 256k
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 83 of 120 register name: rdulr register description: rclk disable upon los register address (lius 1 ? 8): 16h bit # 7 6 5 4 3 2 1 0 name rdulr8 rdulr7 rdulr6 rdulr5 rdulr4 rdulr3 rdulr2 rdulr1 def ault 0 0 0 0 0 0 0 0 register address (lius 9 ? 16): 36h bit # 7 6 5 4 3 2 1 0 name rdulr16 rdulr15 rdulr14 rdulr13 rdulr12 rdulr11 rdulr10 rdulr9 default 0 0 0 0 0 0 0 0 bits 7 to 0: rclk disable upon los register n (rdulr n ). when this bit is set th e rclk for channel n is disabled upon a loss of signal and set as a low output. when reset or default rclk will switch to mclk upon a loss of signal within 10ms. register name: gisc register description: global interrupt status control register address : 1eh bit # 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? intm cwe default 0 0 0 0 0 0 0 0 bit 1: int pin mode (intm). this bit determines the inactive mode of the int pin. the int pin always drives low when active. 0 = pin is high impedance when not active. 1 = pin drives high when not active. bit 0: clear on write enable (cwe). when this bit is set the clear on write is enabled for all the latched interrupt status registers. the host processor must write a 1 to the latched interrupt status register bit positi on before the particular bit will be cleared. default for all the latched interrupt status registers is to clear on a read.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 84 of 120 6.1.4 bert registers register name: bcr register description: bert control register address (lius 1 ? 8): 00h register address (lius 9 ? 16): 20h bit # 7 6 5 4 3 2 1 0 name pmum lpmu rnpl rpic mpr aprd tnpl tpic default 0 0 0 0 0 0 0 0 bit 7: performance monitoring update mode (pmum). when 0, a performance monitoring update is initiated by the lpmu register bit. when 1, a performance monitoring update is initiated by the receive performance monitoring update signal (rpmu). note: if rpmu or lpmu is one, changing the state of this bit may cause a performance monitoring update to occur. bit 6: local performance monitoring update (lpmu). t his bit causes a performance monitoring update to be initiated if local performance monitoring update is enabled (pmum = 0) . a 0 -to - 1 transition causes the performance monitoring registers to be updated with the latest data, and the counters reset (0 or 1) . for a second performance monitoring update to be initiated, this bit must be set to 0, and back to 1 . if lpmu goes low before the pms bit goes high, an update might not be performed . this bit has no affect when pmum = 1. bit 5: receive new pattern load ( rnpl). a 0 -to - 1 transition of this bit will cause the programmed test pattern (qrss, pts, plf[4:0], ptf[4:0], and bsp[31:0]) to be loaded in to the receive pattern generator. this bit must be changed to zero and back to one for another pattern to be loaded . loading a new pattern will forces the receive pattern generator out of the ?sync? state which causes a resynchronization to be initiated. note: qrss, pts, plf[4:0], ptf[4:0], and bsp[31:0] must not change from the time this bit transitions from 0 to 1 un til four rxck clock cycles after this bit transitions from 0 to 1. bit 4: receive pattern inversion control (rpic). when 0, the receive incoming data stream is not altered. when 1, the receive incoming data stream is inverted . bit 3: manual pattern resynch ronization (mpr). a zero to one transition of this bit will cause the receive pattern generator to resynchronize to the incoming pattern. this bit must be changed to zero and back to one for another resynchronization to be initiated. note: a manual resynch ronization forces the receive pattern generator out of the ?sync? state. bit 2: automatic pattern resynchronization disable (aprd). when 0, the receive pattern generator will automatically resynchronize to the incoming pattern if six or more times during t he current 64 - bit window the incoming data stream bit and the receive pattern generator output bit did not match. when 1, the receive pattern generator will not automatically resynchronize to the incoming pattern . note: automatic synchronization is prevent ed by not allowing the receive pattern generator to automatically exit the ?sync? state. bit 1: transmit new pattern load (tnpl). a 0 - to - 1 transition of this bit will cause the programmed test pattern (qrss, pts, plf[4:0], ptf[4:0], and bsp[31:0]) to be lo aded in to the transmit pattern generator. this bit must be changed to zero and back to one for another pattern to be loaded. note: qrss, pts, plf[4:0], ptf[4:0], and bsp[31:0] must not change from the time this bit transitions from 0 to 1 until four txck clock cycles after this bit transitions from 0 to 1. bit 0: transmit pattern inversion control (tpic). when 0, the transmit outgoing data stream is not altered. when 1, the transmit outgoing data stream is inverted .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 85 of 120 register name: bpcr1 register descrip tion: bert pattern configuration register 1 register address (lius 1 ? 8): 02h register address (lius 9 ? 16): 22h bit # 7 6 5 4 3 2 1 0 name ? qrss pts plf4 plf3 plf2 plf1 plf0 default 0 0 0 0 0 0 0 0 bit 6: qrss enable (qrss). when 0, the pattern gen erator configuration is controlled by pts, plf[4:0], and ptf[4:0], and bsp[31:0]. when 1, the pattern generator configuration is forced to a prbs pattern with a generating polynomial of x 20 + x 17 + 1. the output of the pattern generator will be forced to o ne if the next fourteen output bits are all zero. bit 5: pattern type select (pts). when 0, the pattern is a prbs pattern. when 1, the pattern is a repetitive pattern . bits 4 to 0: pattern length feedback (plf[4:0]). these five bits control the ?length? fe edback of the pattern generator. the ?length? feedback will be from bit n of the pattern generator (n = plf[4:0] +1). for a prbs signal, the feedback is an xor of bit n and bit y. for a repetitive pattern the feedback is bit n. register name: bpcr2 regi ster description: bert pattern configuration register 2 register address (lius 1 ? 8): 03h register address (lius 9 ? 16): 23h bit # 7 6 5 4 3 2 1 0 name ? ? ? ptf4 ptf3 ptf2 ptf1 ptf0 default 0 0 0 0 0 0 0 0 bits 4 to 0: pattern tap feedback (ptf[4:0] ). these five bits control the prbs ?tap? feedback of the pattern generator. the ?tap? feedback will be from bit y of the pattern generator (y = ptf[4:0] +1). these bits are ignored when programmed for a repetitive pattern. for a prbs signal, the feedback is an xor of bit n and bit y.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 86 of 120 register name: bspr1 register description: bert seed/pattern register 1 register address (lius 1 ? 8): 04h register address (lius 9 ? 16): 24h bit # 7 6 5 4 3 2 1 0 name bsp7 bsp6 bsp5 bsp4 bsp3 bsp2 bsp1 bsp0 default 0 0 0 0 0 0 0 0 register name: bspr2 register description: bert seed/pattern register 2 register address (lius 1 ? 8): 05h register address (lius 9 ? 16): 25h bit # 7 6 5 4 3 2 1 0 name bsp15 bsp14 bsp13 bsp12 bsp11 bsp10 bsp9 bsp8 default 0 0 0 0 0 0 0 0 register name: bspr3 register description: bert seed/pattern register 3 register address (lius 1 ? 8): 06h register address (lius 9 ? 16): 26h bit # 7 6 5 4 3 2 1 0 name bsp23 bsp22 bsp21 bsp20 bsp19 bsp18 bsp17 bsp16 default 0 0 0 0 0 0 0 0 regis ter name: bspr4 register description: bert seed/pattern register 4 register address (lius 1 ? 8): 07h register address (lius 9 ? 16): 27h bit # 7 6 5 4 3 2 1 0 name bsp31 bsp30 bsp29 bsp28 bsp27 bsp26 bsp25 bsp24 default 0 0 0 0 0 0 0 0 bits 31 to 0: bert seed/pattern (bsp[31:0]). these 32 bits are the programmable seed for a transmit prbs pattern, or the programmable pattern for a transmit or receive repetitive pattern. bsp(31) will be the first bit output on the transmit side for a 32 - bit repetitive pattern or 32- bit length prbs. bsp(31) will be the first bit input on the receive side for a 32 - bit repetitive pattern.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 87 of 120 register name: teicr register description: transmit error insertion control register register address (lius 1 ? 8): 08h register addr ess (lius 9 ? 16): 28h bit # 7 6 5 4 3 2 1 0 name ? ? teir2 teir1 teir0 bei tsei meims default 0 0 0 0 0 0 0 0 bits 5 to 3: transmit error insertion rate (teir[2:0]). these three bits indicate the rate at which errors are inserted in the output data st ream . one out of every 10 n bits is inverted. teir[2:0] is the value n. a teir[2:0] value of 0 disables error insertion at a specific rate. a teir[2:0] value of 1 result in every 10th bit being inverted. a teir[2:0] value of 2 result in every 100th bit bein g inverted. error insertion starts when this register is written to with a teir[2:0] value that is nonzero. if this register is written to during the middle of an error insertion process, the new error rate will be started after the next error is inserted. bit 2: bit error insertion enable (bei). when 0, single bit error insertion is disabled. when 1, single bit error insertion is enabled. bit 1: transmit single error insert (tsei). this bit causes a bit error to be inserted in the transmit data stream if m anual error insertion is disabled (meims = 0) and single bit error insertion is enabled . a 0 to 1 transition causes a single bit error to be inserted. for a second bit error to be inserted, this bit must be set to 0, and back to 1. note: if meims is low, a nd this bit transitions more than once between error insertion opportunities, only one error will be inserted. bit 0: manual error insert mode select (meims). when 0, error insertion is initiated by the tsei register bit. when 1, error insertion is initiat ed by the transmit manual error insertion signal (tmei). note: if tmei or tsei is one, changing the state of this bit may cause a bit error to be inserted. register name: bsr register description: bert status register address (lius 1 ? 8): 0ch register address (lius 9 ? 16): 2ch bit # 7 6 5 4 3 2 1 0 name ? ? ? ? pms ? bec oos default 0 0 0 0 0 0 0 0 bit 3: performance monitoring update status (pms). t his bit indicates the status of the receive performance monitoring register (counters) update. this bit will transition from low to high when the update is completed. pms is asynchronously forced low when the lpmu bit (pmum = 0) or rpmu signal (pmum=1) goes low . bit 1: bit error count (bec). when 0, the bit error count is zero . when 1, the bit error cou nt is one or more. bit 0: out of synchronization (oos). when 0, the receive pattern generator is synchronized to the incoming pattern. when 1, the receive pattern generator is not synchronized to the incoming pattern.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 88 of 120 register name: bsrl register descri ption: bert status register latched register address (lius 1 ? 8): 0eh register address (lius 9 ? 16): 2eh bit # 7 6 5 4 3 2 1 0 name ? ? ? ? pmsl bel becl oosl default 0 0 0 0 0 0 0 0 bit 3: performance monitoring update status latched (pmsl). this bi t is set when the pms bit transitions from 0 to 1. a read operation clears this bit. bit 2: bit error latched (bel). this bit is set when a bit error is detected . a read operation clears this bit. bit 1: bit error count latched (becl). this bit is set when the bec bit transitions from 0 to 1. a read operation clears this bit. bit 0: out of synchronization latched (oosl). this bit is set when the oos bit changes state. a read operation clears this bit. register name: bsrie register description: bert statu s register interrupt enable register address (lius 1 ? 8): 10h register address (lius 9 ? 16): 30h bit # 7 6 5 4 3 2 1 0 name ? ? ? ? pmsie beie becie oosie default 0 0 0 0 0 0 0 0 bit 3: performance monitoring update status interrupt enable (pmsie). t his bit enables an interrupt if the pmsl bit is set. 0 = interrupt disabled 1 = interrupt enabled bit 2: bit error interrupt enable (beie). this bit enables an interrupt if the bel bit is set. 0 = interrupt disabled 1 = interrupt enabled bit 1: bit err or count interrupt enable (becie). this bit enables an interrupt if the becl bit is set. 0 = interrupt disabled 1 = interrupt enabled bit 0: out of synchronization interrupt enable (oosie). this bit enables an interrupt if the oosl bit is set. 0 = inter rupt disabled 1 = interrupt enabled
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 89 of 120 register name: rbecr1 register description: receive bert bit error count register 1 register address (lius 1 ? 8): 14h register address (lius 9 ? 16): 34h bit # 7 6 5 4 3 2 1 0 name bec7 bec6 bec5 bec4 bec3 bec2 bec 1 bec0 default 0 0 0 0 0 0 0 0 register name: rbecr2 register description: receive bert bit error count register 2 register address (lius 1 ? 8): 15h register address (lius 9 ? 16): 35h bit # 7 6 5 4 3 2 1 0 name bec15 bec14 bec13 bec12 bec11 bec10 be c9 bec8 default 0 0 0 0 0 0 0 0 register name: rbecr3 register description: receive bert bit error count register 3 register address (lius 1 ? 8): 16h register address (lius 9 ? 16): 36h bit # 7 6 5 4 3 2 1 0 name bec23 bec22 bec21 bec20 bec19 bec18 b ec17 bec16 default 0 0 0 0 0 0 0 0 bits 23 to 0: bert bit error count (bec[23:0]). these 24 bits indicate the number of bit errors detected in the incoming data stream. this count stops incrementing when it reaches a count of ff ffffh . the associated bi t error counter will not incremented when an oos condition exists .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 90 of 120 register name: rbcr1 register description: receive bert bit count register 1 register address (lius 1 ? 8): 18h register address (lius 9 ? 16): 38h bit # 7 6 5 4 3 2 1 0 name bc7 bc6 bc 5 bc4 bc3 bc2 bc1 bc0 default 0 0 0 0 0 0 0 0 register name: rbcr2 register description: receive bert bit count register 2 register address (lius 1 ? 8): 19h register address (lius 9 ? 16): 39h bit # 15 14 13 12 11 10 9 8 name bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 default 0 0 0 0 0 0 0 0 register name: rbcr3 register description: receive bert bit count register 3 register address (lius 1 ? 8): 1ah register address (lius 9 ? 16): 3ah bit # 7 6 5 4 3 2 1 0 name bc23 bc22 bc21 bc20 bc19 bc18 bc17 bc1 6 default 0 0 0 0 0 0 0 0 register name: rbcr4 register description: receive bert bit count register 4 register address (lius 1 ? 8): 1bh register address (lius 9 ? 16): 3bh bit # 15 14 13 12 11 10 9 8 name bc31 bc30 bc29 bc28 bc27 bc26 bc25 bc24 def ault 0 0 0 0 0 0 0 0 bits 31 to 0: bert bit count (bc[31:0]). these 32 bits indicate the number of bits in the incoming data stream. this count stops incrementing when it reaches a count of ffff ffffh . the associated bit counter will not incremented when an oos condition exists .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 91 of 120 7 jtag boundary scan a rchitecture and test access port the ds26324 ieee 1149.1 design supports the standard instruction codes sample/preload, bypass, and extest. optional public instructions included are highz, clamp, and idcode. the ds26324 contains the following as required by ieee 1149.1 standard test - access port and boundary - scan architecture: test access port (tap) tap controller instruction register bypass register boundary scan register device identification register detai ls on boundary scan architecture and the test access port can be found in ieee 1149.1 - 1990, ieee 1149.1a - 1993, and ieee 1149.1b- 1994. the test access port has the necessary interface pins: trstb, tclk, tms, tdi, and tdo. see the pin descriptions for detail s. for the latest bsdl files go to www.maxim - ic.com/tools/bsdl/ and search for ds26324. figure 7 - 1 . jtag functional block diagram +v boundary scan register indentification register bypass register instruction register tdi tms tclk trstb tdo +v +v test access port controlle r mux 10k ? 10k ? 10k ? select output enable
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 92 of 120 7.1 tap controller state machine the tap controller is a finite state machine that responds to the logic level at tms on the rising edge of tclk. the state diagram is shown in figure 7 -2 . 7.1.1 test - logic - reset upon power - up, the tap controller will be in the test - logic - reset state. the instruction register will contain the idcode instruction. all system logic of the device will operate normally. this state is automatically entered during power - up. this state is entered from any state if the tms is held high for at least 5 clocks. 7.1.2 run - test - idle the run - test - idle is used between scan operations or during specific tests. the instruction register and test registers will remain idle. the controller remains in this st ate when tms is held low. when the tms is high and rising edge of tclk is applied the controller moves to the select -dr- scan state. 7.1.3 select - dr- scan all test registers retain their previous state. with tms low, a rising edge of tclk moves the controller int o the capture - dr state and will initiate a scan sequence. tms high during a rising edge on tclk moves the controller to the select -ir - scan state. 7.1.4 capture - dr data can be parallel - loaded into the test - data registers if the current instruction is extest or sa mple/preload. if the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its current value. on the rising edge of tclk, the controller will go to the shift - dr state if tms i s low or it will go to the exit1 - dr state if tms is high. 7.1.5 shift - dr the test - data register selected by the current instruction will be connected between tdi and tdo and will shift data one stage towards its serial output on each rising edge of tclk. if a te st register selected by the current instruction is not placed in the serial path, it will maintain its previous state. when the tap controller is in this state and a rising edge of tclk is applied, the controller enters the exit1 - dr state if tms is high or remains in shift - dr state if tms is low. 7.1.6 exit1 - dr while in this state, a rising edge on tclk will put the controller in the update - dr state, which terminates the scanning process, if tms is high. a rising edge on tclk with tms low will put the controller in the pause - dr state. 7.1.7 pause - dr shifting of the test registers is halted while in this state. all test registers selected by the current instruction will retain their previous state. the controller will remain in this state while tms is low. a rising edge on tclk with tms high will put the controller in the exit2 - dr state. 7.1.8 exit2 - dr a rising edge on tclk with tms high while in this state will put the controller in the update - dr state and terminate the scanning process. a rising edge on tclk with tms low will enter the shift - dr state. 7.1.9 update - dr a falling edge on tclk while in the update - dr state will latch the data from the shift register path of the test registers into the data output latches. this prevents changes at the parallel output due to changes in the shift register.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 93 of 120 7.1.10 select - ir - scan all test registers retain their previous state. the instruction register will remain unchanged during this state. with tms low, a rising edge on tclk moves the controller into the capture - ir state and will initiate a scan s equence for the instruction register. tms high during a rising edge on tclk puts the controller back into the test - logic - reset state. 7.1.11 capture - ir the capture - ir state is used to load the shift register in the instruction register with a fixed value. this va lue is loaded on the rising edge of tclk. if tms is high on the rising edge of tclk, the controller will enter the exit1 - ir state. if tms is low on the rising edge of tclk, the controller will enter the shift - ir state. 7.1.12 shift - ir in this state, the shift reg ister in the instruction register is connected between tdi and tdo and shifts data one stage for every rising edge of tclk towards the serial output. the parallel registers as well as all test registers remain at their previous states. a rising edge on tcl k with tms high will move the controller to the exit1 - ir state. a rising edge on tclk with tms low will keep the controller in the shift - ir state while moving data one stage thorough the instruction shift register. 7.1.13 exit1 - ir a rising edge on tclk with tms l ow will put the controller in the pause - ir state. if tms is high on the rising edge of tclk, the controller will enter the update - ir state and terminate the scanning process. 7.1.14 pause - ir shifting of the instruction shift register is halted temporarily. with t ms high, a rising edge on tclk will put the controller in the exit2 - ir state. the controller will remain in the pause - ir state if tms is low during a rising edge on tclk. 7.1.15 exit2 - ir a rising edge on tclk with tms high will put the controller in the update -ir state. the controller will loop back to shift - ir if tms is low during a rising edge of tclk in this state. 7.1.16 update - ir the instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of tclk as the co ntroller enters this state. once latched, this instruction becomes the current instruction. a rising edge on tclk with tms low will put the controller in the run - test - idle state. with tms high, the controller will enter the select -dr- scan state.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 94 of 120 figure 7 - 2 . tap controller state diagram 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 select dr-scan capture dr shift dr exit dr pause dr exit2 dr update dr select ir-scan capture ir shift ir exit ir pause ir exit2 ir update ir test logic reset run test/ idle 0
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 95 of 120 7.2 instruction register the instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. when the tap controller enters the shift - ir state, the instruction shift register will be connected between tdi and tdo. while in the shift - ir state, a rising edge on tclk with tms low will shift the data one stage towards the serial output at tdo. a rising edge on tclk in the exit1 - ir stat e or the exit2 - ir state with tms high will move the controller to the update - ir state. the falling edge of that same tclk will latch the data in the instruction shift register to the instruction parallel output. instructions supported by the ds26324 and it s respective operational binary codes are shown in table 7 -1 . table 7 - 1 . instruction codes for ieee 1149.1 architecture instruction selected register instructio n codes extest boundary scan 000 highz bypass 010 clamp bypass 011 sample/preload boundary scan 100 idcode device identification 110 bypass bypass 111 7.2.1 extest this allows testing of all interconnections to the device. when the extest instruction is l atched in the instruction register, the following actions occur. once enabled via the update - ir state, the parallel outputs of all digital output pins will be driven. the boundary scan register will be connected between tdi and tdo. the capture - dr will sam ple all digital inputs into the boundary scan register. 7.2.2 highz all digital outputs of the device will be placed in a high - impedance state. the bypass register will be connected between tdi and tdo. 7.2.3 clamp all digital outputs of the device will output data fr om the boundary scan parallel output while connecting the bypass register between tdi and tdo. the outputs will not change during the clamp instruction. 7.2.4 sample/preload this is a mandatory instruction for the ieee 1149.1 specification that supports two func tions. the digital i/os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the capture - dr state. sample/preload also allows the device to shift data into the boundary scan registe r via tdi using the shift - dr state. 7.2.5 idcode when the idcode instruction is latched into the parallel instruction register, the identification test register is selected. the device identification code will be loaded into the identification register on the ri sing edge of tclk following entry into the capture - dr state. shift - dr can be used to shift the identification code out serially via tdo. during test - logic - reset, the identification code is forced into the instruction register?s parallel output. the id code will always have a 1 in the lsb position. the next 11 bits identify the manufacturer?s jedec number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version table 7 -2 . table 7 -3 lists the device id code for the ds26324. 7.2.6 bypass when the bypass instruction is latched into the parallel instruction register, tdi connects to tdo through the one- bit test bypass register. this allo ws data to pass from tdi to tdo not affecting the device?s normal operation.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 96 of 120 table 7 - 2 . id code structure msb lsb version contact factory device id jedec 1 4 bits 16 bits 00010100001 1 table 7 - 3 . device id codes device 16- bit id ds26324 003ch 7.3 test registers ieee 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. an optional test register has been included with the ds26324 design. this test register is the identification register and is used with the idcode instruction and the test - logic - reset state of the tap controller. 7.3.1 boundary scan register this register contains both a shift register path and a latched parallel output for all control cells and digital i/o cells and is n bits in length. 7.3.2 bypass register this register is a single 1 - bit shift register used with the bypass, clamp, and highz instructions that provide a short path between tdi and tdo. 7.3.3 identifi cation register the identification register contains a 32 - bit shift register and a 32- bit latched parallel output. this register is selected during the idcode instruction and when the tap controller is in the test - logic - reset state. see table 7 -2 and table 7 -3 for more information about bit usage.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 97 of 120 8 dc electrical charac terization absolute maximum rat ings voltage range on any lead with respect to v ss (except v dd )?? ???????????????. - 0.3v to +5.5v supply voltage (v dd ) range with respect to v ss ?..????????????????????? - 0.3v to +3.63v operating temperature range for DS26324G????????????????????????..0c to +70c operating temperature range for DS26324Gn??????????????????. .????.. - 40c to +85c storage temperature?????????????????????????????????? - 55c to +125c soldering t emperature (reflow) l ead(pb) - free ........................................................................................................................................ +260 c c ontaining lead(pb) ............................................................................................................................... +240 c this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. 8.1 dc pin logic levels table 8 - 1 . recommended dc operating conditions (t a = - 40c to +85c for DS26324Gn.) parameter symbol min typ max units notes logic 1 v ih 2.0 5.5 v logic 0 v il - 0.3 +0.8 v supply v dd 3.135 3.3 3.465 v table 8 - 2 . pin capacitance (t a = +25c) parameter symbol min typ max units notes input capacitance c in 7 pf output capacitance c out 7 pf 8.2 su pply current and output voltage table 8 - 3 . dc characteristics (v dd = 3.135 to 3.465v, t a = - 40c to +85c.) (note 1) parameter symbol min typ max units notes supply current at 3.465v i dd 1100 ma 2, 3 suppl y current at 3.3v 500 input leakage i il - 10.0 +10.0 a tri - state output leakage i ol - 10.0 +10.0 a output voltage (i o = ? 4.0ma) v oh 2.4 v output voltage (i o = +4.0ma) v ol 0.4 v note 1: specifications to - 40 c are guaranteed by design ( gbd) and not production tested. note 2: rclk1 - n = tclk1- n = 1.544mhz. note 3: power dissipation with all ports active, ttip and tring driving a 25 ? load, for an all - ones data density.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 98 of 120 9 ac timing characteri stics 9.1 line interface characteristics table 9 - 1 . transmitter characteristics parameter symbol min typ max units notes output mark amplitude e1 75 ? v m 2.14 2.37 2.6 v e1 120 ? 2.7 3.0 3.3 t1 100 ? 2.4 3.0 3.6 t1 110 ? 2.4 3.0 3.6 output zero am plitude v s - 0.3 +0.3 v 1 transmit amplitude variation with supply -1 +1 % transmit path delay single - rail 8 ui dual -rail 3 table 9 - 2 . receiver characteristics parameter symbol min typ max un its notes cable attenuation attn 12 db analog loss -of - signal threshold 200 mv 1 hysteresis short - haul mode 100 mv allowable zeros before loss 192 2 192 2048 allowable ones before loss 24 3 192 192 receive path delay single - rail 8 ui dual -rail 3 note 1: measured at the rring and rtip pins. note 2: 192 zeros for t1 and t1.231 specification compliance; 192 zeros for e1 and g.775 specification compliance; 2048 zeros for ets 300 233 compliance. n ote 3: 24 ones in 192 - bit period for t1.231; 192 ones for g.775; 192 ones for ets 300 233.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 99 of 120 9.2 parallel host interface timing characteristics the following tables show the ac characteristics for the external bus interface. table 9 - 3 . intel read mode characteristics (v dd = 3.3v 5%, t j = - 40c to +125c.) (note 1) (see figure 9 -1 and figure 9 -2 .) signal name(s ) symbol description min typ max units notes rdb t1 pulse width if not using rdyb 40 ns 2 csb t2 setup time to rdb 0 ns 2 csb t3 hold time from rdb 0 ns 2 ad[7:0] t4 setup time to ale 2 ns 2 a[5:0] t5 hold time from rdb 0 ns 2 d[7:0], ad[7: 0] t6 delay time rdb, csb active 40 ns 2 d[7:0], ad[7:0] t7 deassert delay from rdb, csb inactive 2 20 ns 2 rdyb t8 enable delay time from csb active 20 ns 2 rdyb t9 disable delay time from the csb inactive 15 ns 2 ad[7:0] t10 hold time from ale 3 ns 2 ale t11 pulse width 5 ns 2 d[7:0] t12 output delay from ale latched 40 ns 2 a[5:0] t13 setup time to rdb 10 ns 2 rdyb t14 delay time from rdb 0 ns 2 rdyb t15 active output delay time from rdb 10 35 ns 2 note 1: the timing paramet ers in this table are guaranteed by design (gbd). note 2: the input/output timing reference level for all signals is v dd /2.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 1 00 of 120 figure 9 - 1 . intel nonmuxed read cycle a[5:0] rdb csb d[7:0] ale=(1) address data out t1 t13 t3 t7 t15 t8 t5 t9 t2 t6 t14 rdyb
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 101 of 120 figure 9 - 2 . intel mux read cycle rdb csb ad[7:0] ale address data out t1 t12 t3 t7 t15 t8 t9 t2 t6 t14 t11 t10 t4 rdyb
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 102 of 120 table 9 - 4 . intel write cycle characteristics (v dd = 3.3v 5%, t j = - 40c to +125c.) (note 1) (see figure 9 -3 and figure 9 -4 .) signal name(s) symbol description min typ max units notes wrb t1 pulse width 40 ns 2 csb t2 setup time to wrb 0 ns 2 csb t3 hold time to wrb 0 ns 2 ad[7:0] t4 setup time to ale 2 ns 2 a[5:0] t5 hold time from wrb 0 ns 2 d[7:0], ad[7:0] t6 input setup time to wrb 10 ns 2 d[7:0], ad[7:0] t7 input hold time to wrb 5 ns 2 rdyb t8 enable delay from csb active 20 ns 2 rdyb t9 delay time from wrb active 10 ns 2 rdyb t1 0 delay time from wrb inactive 0 ns 2 rdyb t11 disable delay time from csb inactive 15 ns 2 ale t12 pulse width 5 ns 2 ad[7:0] t13 hold time from ale inactive 3 ns 2 a[5:0] t14 valid address to wrb inactive 35 ns 2 note 1: the timing parame ters in this table are guaranteed by design (gbd). note 2: the input/output timing reference level for all signals is v dd /2.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 103 of 120 figure 9 - 3 . intel nonmux write cycle a[5:0] wrb csb d[7:0] ale=(1) address write data t1 t14 t3 t7 t9 t5 t11 t2 t6 t10 t8 rdyb
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 104 of 120 figure 9 - 4 . intel mux write cycle wrb csb ad[7:0] ale address write data t1 t3 t7 t2 t12 t13 t4 t6 t9 t8 t11 t10 rdyb
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 105 of 120 table 9 - 5 . motorola read cycle characteristics (v dd = 3.3v 5%, t j = - 40c to +125c.) (note 1) (see figure 9 -5 and figure 9 -6 .) signal name(s) symbol description min typ max units notes dsb t1 pulse width 40 ns 2 csb t2 setup time to dsb active 0 ns 2 csb t3 hold time from dsb inactive 0 ns 2 rwb t4 set up time to dsb active 0 ns 2 rwb t5 hold time from dsb inactive 0 ns 2 ad[7:0] t6 setup time to asb active 2 ns 2 ad[7:0] t7 hold time to asb inactive 3 ns 2 ad[7:0], d[7:0] t8 output delay time from dsb active 40 ns 2 ad[7:0], d[7:0] t10 ou tput valid delay time from dsb inactive 2 20 ns 2 ackb t11 output delay time from csb inactive 15 ns 2 ackb t12 output delay time from dsb inactive 0 ns 2 ackb t13 enable output delay time from dsb active 20 ns 2 ackb t14 output delay time from dsb active 10 35 ns 2 a[5:0] t15 hold time from dsb inactive 0 ns 2 a[5:0] t16 setup time to dsb active 10 ns 2 note 1: the timing parameters in this table are guaranteed by design (gbd). note 2: the input/output timing reference level for all si gnals is v dd /2.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 106 of 120 figure 9 - 5 . motorola nonmux read cycle a[5:0] dsb csb d[7:0] asb=(1) address data out t1 t16 t3 t10 t15 t2 rwb t8 t4 t5 t14 t11 t12 ackb t13
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 107 of 120 figure 9 - 6 . motorola mux read cycle dsb csb ad[7:0] asb data out t1 t3 t10 t2 rwb t4 t5 address t14 t7 t8 t6 t14 t11 t12 ackb t13
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 108 of 120 table 9 - 6 . m otorola write cycle characteristics (v dd = 3.3v 5%, t j = - 40c to +125c.) (note 1) (see figure 9 -7 and figure 9 -8 .) signal name(s) symbol description min typ max units notes dsb t1 pulse width 35 ns 2 csb t2 setup time to dsb active 0 ns 2 csb t3 hold time from dsb inactive 0 ns 2 rwb t4 setup time to dsb active 0 ns 2 rwb t5 hold time to dsb inactive 0 ns 2 ad[7:0] t6 setup time to asb active 2 ns 2 ad[7:0] t7 hold time from asb active 3 ns 2 ad[7:0], d[7:0] t8 setup time to dsb inactive 10 ns 2 ad[7:0], d[7:0] t9 hold time from dsb inactive 5 ns 2 a[5:0] t10 setup time to dsb active 10 ns 2 ackb t11 output delay from csb inactive 15 ns 2 ackb t12 output delay from dsb inactive 0 ns 2 ackb t13 output enable delay time from dsb active 20 ns 2 ackb t14 output delay time from dsb active 10 ns 2 a[5:0] t15 hold time from dsb 0 ns 2 note 1: the timing parameters in this table are guaranteed by design (gbd). note 2: the input/output timing reference level for all signals is v dd /2.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 109 of 120 figure 9 - 7 . motorola nonmux write cycle a[5:0] dsb csb d[7:0] asb=(1) address write data t1 t10 t3 t9 t15 t2 rwb t4 t5 t8 t14 t11 t12 ackb t13
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 110 of 120 figure 9 - 8 . motorola mux write cycle dsb csb ad[7:0] address write data t1 t3 t9 t2 rwb t4 t5 t8 asb t7 t6 t13 t14 t11 t12 ackb t13
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 111 of 120 9.3 serial port table 9 - 7 . serial port timing characteristics (see figure 9 -9 , figure 9 -10 , and figure 9 -11 .) parameter symbol min typ max units notes sclk high time t1 25 ns sclk low time t2 25 ns active csb to sclk setup time t3 50 ns last sclk to csb inactive time t4 50 ns csb idle time t5 50 ns sdi to sclk setup time t6 5 ns sclk to sdi hold time t7 5 ns sclk falling edge to sdo high impedance (clke = 0); csb rising to sdo high impedance (clke = 1) t8 100 ns figure 9 - 9 . serial bus timing write operation sclk sdi csb t3 t6 t4 t5 lsb msb t2 t1 t7 figure 9 - 10 . serial bus timing read operation with clke = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sclk csb sdo t4 t8 fi gure 9 - 11 . serial bus timing read operation with clke = 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sclk csb sdo t4 t8
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 112 of 120 9.4 system timing table 9 - 8 . transmitter system timing (see figure 9 -12 .) parameter symbol min typ max units notes tpos, tneg setup time with respect to tclk falling edge t1 40 ns tpos, tneg hold time with respect to tclk falling edge t2 40 ns tclk pulse - width high t3 75 ns tclk pulse - width low t4 75 ns tclk period t5 488 ns 648 tclk rise time t6 25 ns tclk fall time t7 25 ns figure 9 - 12 . transmitter systems timing tpos, tneg t1 tclk t2 t3 t4 t5 t6 t7
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 113 of 120 table 9 - 9 . receiver system timing (see figure 9 -13 .) parameter symbol min typ max units notes delay rclk to rpos, rneg valid t1 50 ns delay rclk t o cv valid in single - rail mode t2 50 ns rclk pulse - width high t3 200 ns rclk pulse - width low t4 200 ns rclk period t5 488 ns 648 figure 9 - 13 . receiver systems timing t1 t2 t5 t3 t4 rclk rclk rpos,rneg cv bpv/ exz/ cv bpv/ exz/ cv 1 2 notes: 1) clke = 1. 2) clke = 0.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 114 of 120 9.5 jtag timing t able 9 - 10 . jtag timing characteristics (see figure 9 -14 .) parameter symbol min typ max units notes tck period t1 100 ns tms and tdi setup to tck t2 25 ns tms and tdi hold to tck t3 25 ns tck to tdo hold t4 50 ns figure 9 - 14 . jtag timing tck tms tdi tdo t1 t2 t3 t4
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 115 of 120 10 pin configuration figure 10- 1 . 256 - ball te - csbga 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a rtip1 rring1 modesel rtip16 vddt16 ttip16 ttip15 vddt15 rtip15 vddt14 ttip14 ttip13 vddt13 rtip14 tdo rtip13 b avdd avss motel rring16 rstb tring16 tring15 los14 rring15 los13 tring14 tring13 tms rring14 tdi rring13 c rtip2 rring2 tneg1 a4 tneg16 tneg15 rneg15 rpos15 rneg14 rpos14 tclk13 rpos13 sdo/rdy/ackb tpos12 avss avdd d vddt1 los1 rclk1 gndt1 tpos16 gndt16 intb gndt15 gndt14 gndt13 tclk16 tclk14 gndt12 tck rring12 rtip12 e ttip1 tring1 rneg1 a5 rpos16 rclk16 tpos14 rclk13 rclk14 rneg13 los15 tclk12 tneg12 rpos12 trstb vddt12 f ttip2 tring2 rpos2 rpos1 tclk1 tpos1 tneg14 rclk15 tpos13 los16 rneg12 r clk12 rneg11 tclk11 tring12 ttip12 g vddt2 los2 a2 tclk2 rneg2 rclk2 tpos2 tneg13 tclk3 tneg4 tpos11 rpos11 rclk11 sdi/wrb/dsb tring11 ttip11 h rtip3 rring3 a1 gndt2 a3 tclk4 avdd dvdd dvss avss tneg11 mclk gndt11 rdb/rw b los12 vddt11 j vddt3 los3 rneg16 gndt3 tneg3 tpos3 avss dvss dvdd avdd tpos10 tneg10 gndt10 tneg2 rring11 rtip11 k ttip3 tring3 rclk3 rneg3 rclk4 tpos4 d3 rpos5 tneg8 rneg8 tclk9 tclk10 rpos10 rclk10 los11 vddt10 l t tip4 tring4 rpos3 rpos4 d4 d0 rneg5 tclk6 tpos5 tclk7 tpos9 tneg9 rclk9 rneg10 tring10 ttip10 m vddt4 los4 rneg4 d5 d1 tneg5 tclk5 rclk6 rpos6 rneg6 tpos8 rpos8 rneg9 rpos9 tring9 ttip9 n rtip4 rring4 d7 gndt4 tpos6 g ndt5 tclk15 gndt6 gndt7 a0 gndt8 tpos15 gndt9 sclk/ale/asb los10 vddt9 p avdd avss d6 d2 rclk5 tneg6 tneg7 rpos7 tclk8 rclk7 rneg7 tpos7 rclk8 csb rring10 rtip10 r rring5 los5 rring6 los7 tring5 tring6 los8 rring7 resref tring7 tring8 oe rring8 los9 avss avdd t rtip5 los6 rtip6 vddt5 ttip5 ttip6 vddt6 rtip7 vddt7 ttip7 ttip8 vddt8 rtip8 clke/mux rring9 rtip9
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 116 of 120 11 package information for the latest package outline information and land patterns (footprints), go to www.maxim - ic.com /packages . note that a ?+?, ?#?, or ? - ? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 265 te - csbga x256t+2 21-0315 90-0291
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 117 of 120 12 thermal information table 12- 1 . thermal characteristics parameter min typ max v (m/s) notes ambient temperature - 40 c +85 c 1 jun ction temperature +125 c theta - ja ( ja ) in still air conduction 16.6 c/w 0 2 theta - jc ( jc ) conduction 3.0 c/w theta - jb ( jb ) conduction 7.5 c/w theta - ja ( ja ) in forced air 15.0 c/w 0.75 theta - ja ( ja ) in forced air 14.6 c/w 1 .25 theta - ja ( ja ) in forced air 14.0 c/w 2.5 note 1: the package is mounted on a four - layer jedec standard test board. note 2: theta - ja ( ja ) is the junction - to - ambient thermal resistance, when the package is mounted on a four - layer jedec standar d test board. table 12- 2 . package power dissipation (for thermal considerations) mode typical 50% 1s (note 1) typical 100% 1s (note 2) maximum 100% 1s (note 3) fully internal partially internal external ful ly internal partially internal external fully internal partially internal external e1 - 75 ? 1.64 1.43 1.31 2.56 2.15 1.90 2.82 2.36 1.98 e1 - 120 ? 1.49 1.19 1.19 2.23 1.62 1.62 2.54 1.69 1.69 t1 - lbo0 1.87 1.52 1.47 2.96 2.26 2.14 3.56 2.51 2.23 t1 - lbo1 1.9 2 1.57 1.51 3.03 2.32 2.20 3.63 2.57 2.30 t1 - lbo2 1.95 1.60 1.55 3.06 2.35 2.29 3.66 2.60 2.39 t1 - lbo3 1.99 1.63 1.58 3.12 2.41 2.29 3.72 2.67 2.39 t1 - lbo4 2.02 1.67 1.61 3.16 2.46 2.34 3.77 2.72 2.44 j1 - lbo0 1.84 1.49 1.47 2.90 2.20 2.14 3.44 2.36 2.2 3 j1 - lbo1 1.89 1.54 1.51 2.96 2.26 2.20 3.51 2.42 2.30 j1 - lbo2 1.92 1.57 1.55 2.99 2.29 2.29 3.54 2.45 2.39 j1 - lbo3 1.95 1.60 1.58 3.05 2.35 2.29 3.60 2.52 2.39 j1 - lbo4 1.99 1.63 1.61 3.10 2.39 2.34 3.65 2.57 2.44 note 1: typical voltage, transmittin g/receiving 50% 1s in watts. note 2: typical voltage, transmitting/receiving 100% 1s in watts. note 3: maximum voltage, transmitting/receiving 100% 1s in watts. table 12-3 describes how much power to deduct per - channel from the total power dissipation values listed in table 12-2 .
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 118 of 120 table 12- 3 . per - channel power - down savings (for thermal considerations) mode typical 50% 1s (note 1) typical 100% 1s (note 2) maximum 100% 1s (note 3) fully internal partially internal external fully internal partially internal external fully internal partially internal external e1 - 75 ? 0.093 0.080 0.072 0.151 0.125 0.109 0.166 0.137 0.113 e1 - 120 ? 0.084 0.065 0.065 0.130 0.092 0.092 0.148 0.095 0.095 t1 - lbo0 0.108 0.086 0.083 0.176 0.132 0.125 0.213 0.147 0.130 t1 - lbo1 0.111 0.089 0.086 0.180 0.136 0.129 0.217 0.151 0.134 t1 - lbo2 0.113 0.091 0.088 0.182 0.138 0.134 0.219 0.15 3 0.140 t1 - lbo3 0.115 0.093 0.090 0.186 0.142 0.134 0.223 0.157 0.140 t1 - lbo4 0.117 0.095 0.092 0.189 0.145 0.137 0.226 0.160 0.143 j1 - lbo0 0.106 0.084 0.083 0.172 0.128 0.125 0.205 0.137 0.130 j1 - lbo1 0.109 0.087 0.086 0.176 0.132 0.129 0.209 0.141 0. 134 j1 - lbo2 0.111 0.089 0.088 0.178 0.134 0.134 0.211 0.143 0.140 j1 - lbo3 0.113 0.091 0.090 0.182 0.138 0.134 0.215 0.147 0.140 j1 - lbo4 0.115 0.093 0.092 0.185 0.141 0.137 0.218 0.150 0.143 note 1: typical voltage, transmitting/receiving 50% 1s in wat ts. note 2: typical voltage, transmitting/receiving 100% 1s in watts. note 3: maximum voltage, transmitting/receiving 100% 1s in watts. t a c + ja x power dissipation maximum junction temperature where: t a = maximum ambient temperature example: t a = +70 c mode = typical 100% 1s e1 -75 ? , fully internal impedance matching air flow = 1.25m/s 70 c + 14.6 c/w x 2.56w = 107 c this is below the maximum junction temperature and, therefore, this solution will support the thermal requirements.
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit 119 of 120 13 data sheet revisi on history revision date description pages changed 070105 initial release. ? 042007 added descriptions of feature enhancements implemented in revision a2: 1) programmable corner frequency for the jitter attenuator in e1 mode. 2) fully internal impedance match ing option for rtip/rring. 3) option for system - side deployment of bert. 4) revised b8zs/hdb3 sections for clarification of functions. 5) added resref pin for receive termination calibration. see below for the detailed list of changes made to this data sheet rev ision. see features bullets, detailed description , and section 5.5.1 for mention of fully internal receive impedance matching. 1, 7, 27 added resref pin (r9). 11 in oe pin description, changed gc.rtctl to tst.rhpmc. 15 deleted r9 from dvss. 16 in section 5.4: transmitter, second paragraph, changed nrz encoding to ami encoding. 20 replaced figure 5 -8 . 25 in table 5 -6 , updated rt; updated section 5.4.3 and section 5.4.4 ; in section 5.4.5: zero suppression ? b8zs or hdb3 , removed ?or transmit maint enance register settings? from last sentence of first paragraph (no such register for this part). 26 changed section 5.4.8 name from drive failure monitor to driver fail monitor ; updated section 5.5 ; added new section 5.5.1: receive impedance matching ca libration. 27 added section 5.5.8: receive dual - rail mode ; added new section 5.5.9: receive single - rail mode ; updated table 5-11. 30 updated section 5.8.2: digital loopback . 33 added new paragraph to section 5.9: bert. 34 changed gmc to bgmc (table 6 - 1) (see also page 53). 40 in table 6 -4 , deleted receive bit error count register 4 (does not exist for this part). 43 in table 6 -5 , changed bit names for loss (lius 1 ? 16) to correctly match bit description on page 49; for tst, changed bits 7 ? 5 from reserved to jabws1, jabws0, and rhpmc (see also page 58). 44 in table 6 -6 , changed srs bit to correctly say srms. 45 in table 6 -7 , added missing address (27) to shlhs for lius 9 ? 16; changed bit 7 and bits 3 ? 0 names for rsmm4 (lius 9 ? 16) to correctly ma tch bit description on page 74; changed ?gisc? (3e) to ?not used? for lius 9 ? 16. 46 in table 6 -8 , changed bsr register bit 3 (pms) to show it is read only (added underline), matching the bit description on page 88, as well as changed ?rw? to ?r? to corre ctly show all bits are read only; changed bsrl register bit 3 (pmsl) to show it is read only (added underline), matching the bit description on page 89, as well as changed ?rl/w? to ?r? to correctly show all bits are read only. 47
ds26324 3.3v, 16 - channel, e1/t1/j1 short - haul line interface unit maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifi cations without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 20 11 maxim integrated products maxim is a registered tradema rk of maxim integrated products, inc. 120 of 120 revision date description pages changed changed gmc to bgmc; ch anged bits 7, 6, and 5 from reserved to bertdir, bmcks, and btcks. 53 in the gc register (lius 1 ? 8), changed bit 7 from reserved to rimpms and bit 2 from rtctl to crimp (see also page 44, table 6 -5 ). 56 in the gc register (lius 9 ? 16), changed bit 7 fro m reserved to rimpms and changed bit 2 from reserved to calen (see also page 44, table 6 -5 ). 57 for tst, changed bits 7, 6, and 5 from reserved to jabws1, jabws0, and rhpmc. 58 in the bit 7 (rimpon) description, changed gc.rtctl to tst.rhpmc; added not e to bit description. 60 changed bit description for oe bits 7 to 0. 61 for ezde, corrected bit names for lius 1 ? 16 from exzde[1:16] to ezde[1:16]; changed bit description to say ?excessive zero detection is only relevant when hdb3 or b8zs decoding is enabled.? for cvdeb, changed bit description to say ?code violation detection is only relevant when hdb3 decoding is enabled (lcs register).? 65 added note to bit 3 (rsmm1:rssm4) description and updated descriptions for bits 6 ? 4 and 2? 0 (deleted ?when? f rom each sentence for clarity). 71, 72, 73, 74 updated package drawing information. 117 in table 12 -1 , deleted ?power dissipation in package?; added new table 12 - 2. package power dissipation (for thermal considerations) and table 12 - 3. per - channel powe r- down saving (for thermal considerations) . 118 053107 table 8 - 3: added ?note 1: specifications to - 40 c are guaranteed by design (gbd) and not production tested.? 97 table 9 - 3, 9 - 4, 9 - 5, and 9 - 6: added ?note 1: the timing parameters in this table are g uaranteed by design (gbd).? 99, 102, 105, 108 012108 changed the gc (2fh) register bit 1 (japs) description. 57 3 / 11 figure 10 - 1 in section 10 pin configuration: corrected cell r9. changed from dvss to resref. 115 pb - free ordering information added 1 table 4 - 1. pin description. trstb function description changed. replaced ?floating? with ?unconnected? 15 section 8 dc electrical characterization: soldering information in absolute maximum ratings table updated 97

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